Abstract: Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.

Abstract: An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.

Abstract: A data packet processing method comprises: receiving data packet including a key message; analyzing the key message; determining whether the data packet is a high priority data packet or a normal data packet according to a result of analyzing the first key message of the data packet; and executing an Rx high priority interrupt in response to determining that the data packet is the high priority data packet. The Rx high priority interrupt is to immediately transmit an interrupt signal to interrupt receiving of the data packets.

Abstract: An electronic device comprising a processing unit and a memory that stores a plurality of program instructions. The processing unit executes the program instructions to perform the following steps: (a) storing pixel data of multiple pixels of a picture in the memory, the number of the pixels being greater than the number of pixels in one horizontal line of the picture; (b) performing an integral image operation on the pixel data to obtain integral image data; (c) storing the integral image data in the memory; (d) using the integral image data to calculate a low-frequency component of a target pixel of the picture; and (e) based on the low-frequency component, selectively performing a temporal noise reduction operation on the target pixel.

Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.

Abstract: An iris image capturing device, an iris image recognition device and an iris image recognition method are provided. Multiple data sequences are captured, in which each data sequence includes an iris image. These data sequences are selected to be a positioning image or an image to be processed. The positioning image is for locating the iris, and the image to be processed is for generating a protected iris image according to where the iris is located in the positioning image.

Abstract: A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.

Abstract: An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.

Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.

Abstract: A headset includes a first sound receiving circuit, a second sound receiving circuit, an adaptive circuit, a first synthesis circuit, and a second synthesis circuit. The adaptive circuit is configured to: obtain a first direction of arrival and a second direction of arrival according to a first sound signal and a second sound signal; obtain a first conversion function and a second conversion function according to the first direction of arrival and the second direction of arrival; obtain a first feed forward audio signal according to the first conversion function and the first sound signal; and obtain a second feed forward audio signal according to the second conversion function and the second sound signal.

Abstract: Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.

Abstract: An IP camera with a wireless relay function includes a lens, a wireless client interface, a wired client interface, a Wi-Fi SoftAP interface, and a bridge interface. The lens receives image data. The wireless client interface transmits the image data to a first wireless client device through a wireless network. The wired client interface transmits the image data to a first wired client device through a wired network. The Wi-Fi SoftAP interface is a virtual interface to be connected to a second wireless client. The bridge interface uses the Wi-Fi SoftAP interface to communicate with the second wireless client, and connects the Wi-Fi SoftAP interface to the wired client interface or the wireless client interface, so that the second wireless client device obtains an IP address and connects to Internet through the wired client interface or the wireless client interface.

Abstract: A method for resetting a memory in the computer system includes turning on the computer system, and a memory controller of the computer system executing a boot code to initialize the memory. After the memory controller executes the boot code, the memory controller updates a programmable initialization code according to the boot code to generate an updated programmable initialization code. After resetting the computer system, the memory controller executes the updated programmable initialization code to restore the memory back to a default state. After the memory is restored to the default state, the memory controller executes the boot code to initialize the memory again. After the memory is initialized, the memory controller controls the memory to perform a normal operation.

Abstract: An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.

Abstract: Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.

Abstract: A semiconductor element fabricated in a semiconductor structure and coupled to an application circuit through at least two connecting terminals. The semiconductor element includes a first spiral coil, a second spiral coil and a connecting portion. The first spiral coil is substantially located in a first metal layer and formed with a first end and a second end. The second spiral coil is substantially located in the first metal layer and formed with a third end and a fourth end. The connecting portion, which is located in a second metal layer, connects the second end and the fourth end. The first end is used as one of the two connecting terminals and the third end is used as the other of the two connecting terminals. The second metal layer is different from the first metal layer.

Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Abstract: Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.

Abstract: A transmitter circuit includes: an in-phase signal processing circuit; a quadrature signal processing circuit; an analog signal processing circuit arranged to operably generate a corresponding analog signal according to the signals outputted from the in-phase signal processing circuit and the quadrature signal processing circuit; a transmitter control circuit arranged to operably control the in-phase signal processing circuit and the quadrature signal processing circuit to cooperate with the analog signal processing circuit to generate a first predetermined signal at a first time point, and to operably control the in-phase signal processing circuit and the quadrature signal processing circuit to cooperate with the analog signal processing circuit to generate a second predetermined signal at a second time point, and an image rejection ratio measurement circuit arranged to operably generate an estimated image rejection ratio of the transmitter circuit.

Abstract: The present invention discloses a wireless communication device including: a transmission circuit generating a digital modulation signal according to transmission data, and analogizing the digital modulation signal to generate and transmit a transmission signal in a first mode; a reception circuit receiving a reception signal including an interference component caused by the transmission circuit; a self-interference cancellation circuit being enabled in the first mode and disabled in a second mode, providing an analog self-interference cancellation signal for the wireless reception circuit according to the transmission signal to cancel a part of the interference component, and providing a digital self-interference cancellation signal for the reception circuit according to the digital modulation signal to cancel another part of the interference component; and a control circuit having the wireless communication device operate in one of the first mode and the second mode according to at least one of indices and