Abstract: A video processing system includes a main chip and a processing chip. The main chip receives first data. The processing chip is coupled to the main chip, and receives second data and to perform a video processing on at least one of the first data transmitted from the main chip and the second data, in order to drive a display panel. First video carried on the first data or second video on the second data has a first resolution, and the first resolution is at least 8K ultra high definition.

Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.

Abstract: A Bluetooth communication system includes: a transmitting-end Bluetooth device arranged to operably insert an auto-pairing request and a source Bluetooth device address into one or more target packets when the transmitting-end Bluetooth device wants to initiate a Bluetooth auto-pairing procedure, and arranged to operably transmit the one or more target packets when operating under a transmitting-end predetermined operating mode; and a receiving-end Bluetooth device arranged to operably receive the one or more target packets when operating under a receiving-end predetermined operating mode, and to parse the one or more target packets to extract the auto-pairing request and the source Bluetooth device address from the one or more target packets. Then, the receiving-end Bluetooth device is enabled to conduct a Bluetooth auto-pairing procedure with the transmitting-end Bluetooth device according to the auto-pairing request and the source Bluetooth device address.

Abstract: A receiver includes a passive CTLE (continuous-time linear equalizer) configured to receive a first voltage signal from a first node and output a current signal to a second node in accordance with a first control signal; a CG (common-gate) amplifier configured to receive the current signal and output a second voltage signal at a third node in accordance with a second control signal; a first active inductor configured to provide an inductive load at the third node; a CS (common-source) CTLE configured to receive the second voltage signal and output a third voltage signal at a fourth node in accordance with a third control signal; a second active inductor configured to provide an inductive load at the fourth node; and a decision circuit configured to receive the third voltage signal and output a decision in accordance with a clock signal.

Abstract: An audio playback device that includes an audio receiver module, a loudspeaker module and an audio control circuit is provided. The audio control circuit includes an interface and a gain adjusting module. The interface receives an audio signal from an audio source. Under a first operation mode, the audio signal is transmitted only to the audio receiver module to be playback. Under a second operation mode, the audio signal is transmitted to the audio receiver module and to the loudspeaker module to be playback. The gain adjusting module includes a temperature sensing circuit to sense a temperature of the audio receiver module and a gain adjusting circuit electrically coupled between the audio interface and the audio receiver module to adjust a gain of the audio signal according to the temperature.

Abstract: Disclosed are an image enhancement method and an image enhancement apparatus which can realize the edge enhancement for an image generated after a demosaicing process according to local characteristics of an input image (i.e. the image sharpening) and can realize the brightness noise suppression and the chroma noise suppression for the image. Thus, by using the image enhancement method and the image enhancement apparatus provided by the present disclosure, clear images can be generated.

Abstract: A Bluetooth Integrated Circuit includes a receiver, a transmitter, and a control circuit. The receiver circuit is configured to receive a scan request packet from an electronic device, and the scan request packet being transmitted by the electronic device in accordance with a Bluetooth wireless low energy standard. The transmitter circuit is configured to transmit a data packet or an advertising packet, and the control circuit is coupled to the receiver circuit and the transmitter circuit. When the receiver circuit receives the scan request packet, the control circuit detects a transmission rate at which the scan request packet is transmitted by the electronic device and controls the transmitter circuit to transmit the data packet or the advertising packet at the data rate related to the scan request packet.

Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

Abstract: A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.

Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.

Abstract: A headset includes a first sound receiving circuit, a second sound receiving circuit, an adaptive circuit, a first synthesis circuit, and a second synthesis circuit. The adaptive circuit is configured to: obtain a first direction of arrival and a second direction of arrival according to a first sound signal and a second sound signal; obtain a first conversion function and a second conversion function according to the first direction of arrival and the second direction of arrival; obtain a first feed forward audio signal according to the first conversion function and the first sound signal; and obtain a second feed forward audio signal according to the second conversion function and the second sound signal.

Abstract: An ODT circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first and second ODTs are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third and the fourth ODTs are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.

Abstract: A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal.

Abstract: A receiver circuit of a transceiver is disclosed including: a calibration circuit arranged to operably perform an I/Q mismatch calibration operation according to an in-phase detection signal and a quadrature detection signal to generate one or more compensation parameters; a parameter storage circuit; an interference detection circuit arranged to operably generate an estimated signal-to-interference ratio according to the in-phase detection signal and the quadrature detection signal; a receiver control circuit arranged to operably determine whether to discard the one or more compensation parameters, wherein the receiver control circuit stores the one or more compensation parameters into the parameter storage circuit only if the estimated signal-to-interference ratio exceeds a predetermined threshold.

Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.

Abstract: An infrared crosstalk compensation method includes capturing an original image of a scene, where the original image includes a plurality of original pixels, the original pixels are arranged in a two-dimensional array according to a first axial direction and a second axial direction, and each original pixel has a red subpixel value, a green subpixel value, a blue subpixel value, and an infrared subpixel value. The method further includes: obtaining compensated values of the red, green, blue, and infrared subpixel values according to the original image, a compensation axial direction, a plurality of red, green, blue compensation coefficients corresponding to the compensation axial direction, and compensation equations; and obtaining a compensated image according to the compensated values of the red, green, blue, and infrared subpixel values.

Abstract: A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.

Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock. The apparatus includes a circuit configured in a ring topology comprising a first switch controlled by a first phase of the input clock, a first inverting amplifier, a second switch controlled by a second phase of the input clock, a second inverting amplifier, a third switch controlled by the first phase of the input clock, a third inverting amplifier, a fourth switch controlled by the second phase of the input clock, and a fourth inverting amplifier, wherein the first inverting amplifier and the third inverting amplifier share a first regenerative load that is reset upon the first phase of the input clock, and the second inverting amplifier and the fourth inverting amplifier share a second regenerative load that is reset upon the second phase of the input clock.

Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.