Patents Assigned to Realtek Semiconductor
  • Patent number: 10615814
    Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Liang-Huan Lei, Shih-Hsiung Huang
  • Patent number: 10614003
    Abstract: A memory card reading method applied to an electronic device, includes: detecting a specification information of a memory card, wherein the specification information includes a transfer speed of the memory; and controlling according to the specification information a reader to host interface to operate in a first operating mode or a second operating mode for reading the memory card, wherein the first operating mode and the second operating mode correspond to different data transfer speeds.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 7, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jiunn-Hung Shiau, Neng-Hsien Lin
  • Patent number: 10614290
    Abstract: The present invention provides an object position determination circuit including a receiving circuit, a detecting circuit and a calculating circuit. In the operations of the object position determination circuit, the receiving circuit is configured to receive an Nth frame and an (N+M)th frame of an image signal, where N is a positive integer, and M is a positive integer greater than one; the detecting circuit is configured to detect positions of an object in the Nth frame and the (N+M)th frame; and the calculating circuit is configured to generate a position of the object in an (N+M+A)th frame according to the positions of the object in the Nth frame and the (N+M)th frame, wherein A is a positive integer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 7, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Teng-Hsiang Yu, Yen-Hsing Wu
  • Patent number: 10608429
    Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 31, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tay-Her Tsaur, Cheng-Cheng Yen, Chien-Ming Wu, Cheng-Pang Chan
  • Patent number: 10605861
    Abstract: The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 31, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Po-Lin Chen, Chun-Yi Kuo, Ying-Yen Chen
  • Patent number: 10598730
    Abstract: A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chihtung Chen, Yi-Te Yeh, Chia-Hsien Cheng, I-Chang Wu, Huai-Yu Yen
  • Patent number: 10601405
    Abstract: The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Cheng Hsu, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 10598726
    Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Huan Lei, Shih-Hsiung Huang, Chih-Lung Chen
  • Patent number: 10601427
    Abstract: A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Kuei Hsu, Ming-Kai Chuang, Mei-Chuan Lu
  • Patent number: 10595232
    Abstract: This invention discloses a method for controlling a wireless communication device to transmit data packets. The method includes steps of: transmitting data packets; counting retry times of data packets in a predetermined time period and generating a result accordingly; comparing said result with a predetermined value and generating a comparison result accordingly; and reducing transmission time of data packets according to said comparison result.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Nan Lin, Wei-Chi Lai, Shen-Chung Lee, Chung-Yao Chang, Wei-Hsuan Chang
  • Patent number: 10591946
    Abstract: A power circuit applied to an electronic device, includes: a control circuit and a power providing circuit, wherein the control circuit is coupled to at least one circuit installed within the electronic device, and is arranged to generate a providing information according to at least one performance indicator of the circuit, wherein the providing information includes an optimal voltage signal setting, and the optimal voltage signal setting is generated according to a performance coefficient corresponding to each performance indicator; the power providing circuit is coupled to the control circuit and the at least one circuit, and is arranged to dynamically provide a voltage signal to the circuit according to the providing information.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chun-Yu Luo, Shih-Chieh Chen, Liang-Hui Li, Yi-Lin Li
  • Patent number: 10593464
    Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10594332
    Abstract: A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Huan Lei, Jian-Ru Lin, Shih-Hsiung Huang
  • Patent number: 10594342
    Abstract: A power amplifying system includes a voltage control oscillator (VCO), a frequency divider, a mixer and an adding amplifier. The VCO is configured to provide an input signal having a frequency that is a non-integer multiple of a predetermined frequency. The frequency divider is coupled to the VCO, and configured to receive the input signal and perform frequency division upon the input signal to respectively generate an in-phase signal and a quadrature signal corresponding to the input signal. The mixer is coupled to the VCO and the frequency divider, and configured to mix the input signal transmitted from the VCO and the in-phase signal transmitted from the frequency divider to output a mixed signal. The adding amplifier is coupled to the mixer and the frequency divider, and configured to integrate the mixed signal and the quadrature signal to generate an output signal having the predetermined frequency.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 17, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ping-Yuan Deng
  • Patent number: 10587303
    Abstract: A transceiver control circuit of a transceiver is disclosed including: a receiver circuit; a transmitter circuit; a shared filtering circuit shared by the receiver circuit and the transmitter circuit; a first mode-switch for switching signal input paths of the shared filtering circuit; a second mode-switch for switching signal output paths of the shared filtering circuit; a mode-switch control circuit for controlling the first mode-switch and the second mode-switch; a short-circuit switch coupled between two output terminals of a filter within the shared filtering circuit; and a short-circuit switch control circuit. In a period during which the transceiver transits from a receiving mode to a transmitting mode, the short-circuit switch control circuit turns on the short-circuit switch for a certain period and then turns off the short-circuit switch.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Sie-Siou Jhang Jian
  • Patent number: 10587436
    Abstract: A signal transmitter device includes a transmitter and a detection circuit. The transmitter is configured to transmit an output signal based on a first baseband signal and a second baseband signal, in which the first baseband signal and the second baseband signal have a baseband frequency. The detection circuit is configured to perform twice signal modulations according to the output signal to detect a signal component, which has the baseband frequency, of the output signal, in order to control a compensation circuit to correct a channel mismatch of the transmitter.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yuan-Shuo Chang
  • Patent number: 10587279
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 10587280
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry, a calibration circuitry, and a randomization circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to least significant bits of an input signal. The second DAC circuit is configured to output a second signal. The calibration circuitry is configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit. The randomization circuitry is configured to randomize most significant bits of the input signal, in order to generate first control signals, in which the second DAC circuit is further configured to generate the second signal according to the most significant bits or the first control signals.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Lung Chen, Shih-Hsiung Huang
  • Patent number: 10587840
    Abstract: The image processing system receives first field information, second field information, and third field information. The first and the third field information correspond to first pixels, and the second field information corresponds to second pixels. The first pixels and the second pixels are disposed in interlaced rows. Generate the motion adaptive deinterlacing parameter of a first pixel by performing the motion detection and interpolation according to the first and the third field information. Calculate the horizontal and the vertical compensating display parameters of the first pixel according to the horizontal and vertical motion estimation values and the first and the third field information. Generate the mixed display parameter of the first pixel by using a weighted average of the horizontal or the vertical compensating display parameter of the first pixel and the motion adaptive deinterlacing parameters of the first pixel.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 10, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ming-Ta Lin
  • Patent number: 10586313
    Abstract: The present disclosure provides an electronic apparatus and an image processing method for image edge enhancement, which adjust each edge pixel located in an image edge of an input image. More specifically, the electronic apparatus and the image processing method adaptively adjust a present pixel that is taken as the edge pixel according to the position of the present pixel in the image edge and the input image, thereby outputting an adjusted pixel value. Accordingly, the electronic apparatus and the image processing method can enhance the image edge according to the actual image condition.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ching-Ju Hsiao, Wen-Tsung Huang