Patents Assigned to Renesas Electronics Corporation
  • Patent number: 11024566
    Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 1, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Akio Ono, Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 11022997
    Abstract: A signal processing device includes an oscillation circuit, a protection target circuit, a delay time detection circuit, and a clock control circuit. The oscillation circuit receives the frequency control signal and generates a clock signal having a frequency corresponding to the frequency control signal. According to the above-mentioned configuration, even when a delay failure due to aging occurs in the signal processing device, it is possible to prevent a malfunction.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 1, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Narihira Takemura, Terunori Kubo, Tetsuo Takahashi
  • Patent number: 11017824
    Abstract: An interference of control signals is caused by a deviation in the start timings of counting between counters of timer counter units of a first MCU and a second MCU. And thus, when a count value of the counter of the MCU of a parent reaches a predetermined value D, the MCU of the parent transmits a trigger signal to the MCU of a child. The MCU of the child obtains the time difference between the start timings of the counts of the counters of the parent and the child from the difference between the D and a count value E of the child at that time. A count period of the child until a maximum value of the count value is reached is adjusted by the time difference.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 25, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuji Tsuda, Yutaka Funabashi, Teruki Fukuyama
  • Patent number: 11019182
    Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 25, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Dnyaneshwar Kulkarni, Thorsten Hoffleit
  • Patent number: 11011668
    Abstract: It is to provide a semiconductor device, a semiconductor system, and a method of controlling the semiconductor device capable of reducing the power consumption. According to one embodiment, a semiconductor device includes a photo coupler control circuit that passes the current to a first signal path for a predetermined period when detecting a change of the input signal supplied from the outside, an insulating circuit that transmits a pulse signal indicating the change of the input signal, from the first signal path to a second signal path insulated from the first signal path, according to the current flow to the first signal path, a holding circuit that generates an input reproducing signal as a reproducing signal of the input signal from the pulse signal transmitted to the second signal path by the insulating circuit, and an internal circuit that receives the input reproducing signal generated by the holding circuit.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tsuyoshi Waki
  • Patent number: 11006855
    Abstract: An ultrasonic receiver receives ultrasonic waves reflected at a plurality of portions of the body of a person to be measured, and thus the person to be measured needs to input the approximate height of himself/herself. An electrostatic capacitance sensor includes a transmission electrode and a reception electrode. The electrostatic capacitance sensor measures a mutual capacitance between the transmission electrode and the reception electrode by a mutual capacitance method. A variable frequency pulse generator generates a pulse supplied to the transmission electrode. A control apparatus allows the variable frequency pulse generator to sweep the frequency of the pulse and allows the electrostatic capacitance sensor to measure the mutual capacitance to identify a frequency at which the measured mutual capacitance is minimized. The control apparatus obtains the height of a person to be measured on the basis of the identified frequency.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kakeru Kimura, Masahito Kajiwara, Shinji Takeda, Takuro Ichikawa, Shoichi Hamada, Koji Hirano
  • Patent number: 11012617
    Abstract: A semiconductor device includes a distortion correction unit that performs correct distortion processing on a captured image, a SRAM that stores image data after the distortion correction processing, a filter processing unit that receives the image data after the distortion correction processing from the SRAM and that performs smoothing filter processing on the image data after the distortion correction processing, after the image data after the distortion correction processing having a size required for the smoothing filter processing is stored in the SRAM, and an image reduction unit that performs reduction processing on image data after the smoothing filter processing.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akihiro Yamamoto
  • Patent number: 11009407
    Abstract: According to one embodiment, a semiconductor device 1 includes a temperature sensor module 10 that outputs a non-linear digital value with respect temperature and a substantial linear sensor voltage value with respect to the temperature, a storage unit 30 that stores the temperature, the digital value, and the sensor voltage value, and a controller 40 that calculates a characteristic formula using the temperature, the digital value, and the sensor voltage value stored in the storage 30, in which the temperature, the digital value, and the sensor voltage value stored in the storage unit 30 include absolute temperature under measurement of absolute temperature, the digital value at the absolute temperature, and the sensor voltage value at the absolute temperature.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanori Ikeda, Tadashi Kameyama
  • Patent number: 11009409
    Abstract: To improve the efficiency of pressure detection, a driver applies a positive-phase signal to a capacitance element from an opposite side to a coupling point in a control device. Another driver applies a reverse-phase signal to another capacitance element from an opposite side to the coupling point. A control unit detects pressures applied to the capacitance elements based on a potential fluctuation at the coupling point.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masato Hirai, Takeshi Yoshizawa, Takeshi Kuwano
  • Patent number: 11012230
    Abstract: A cryptographic communication method using a dynamically-generated private key is provided. A signal generation unit outputs a second signal obtained by giving an error in a predetermined range to a signal obtained based on a first signal. An error correction generation unit outputs a third signal obtained based on the second signal and auxiliary information for correcting an error included in the second signal. A private-key generation unit generates a first private key based on the third signal. An encryption calculation unit outputs an encrypted signal obtained by encrypting a fourth signal based on the first private key.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke Moriyama
  • Patent number: 11004830
    Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 11004749
    Abstract: A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Q 1 and the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Q 2 is formed in the second element region RCM. The first power MOS transistor Q 1 includes a first trench gate electrode TGE1, and the second power MOS transistor Q 2 includes a second trench gate electrode TGE2. The depth GDP1 of the first trench gate electrode TGE1 is shallower than the depth GDP2 of the second trench gate electrode TGE2.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Moriya, Hiroshi Yanagigawa, Kazuhisa Mori
  • Patent number: 11005605
    Abstract: The efficiency of signal transmission is improved. A communication apparatus includes a memory unit, a communication control unit, and an updating unit. A retransmission interval value is stored in the memory unit. The communication control unit transmits a first signal and receives a response signal corresponding to the first signal from a receiver. If the received response signal is a negative response signal, the first signal is retransmitted at a time interval longer than or equal to the retransmission interval value stored in the memory unit, from the transmission of the first signal. The updating unit updates the retransmission interval value stored in the memory unit, according to a time from the transmission of the first signal to the reception of the positive response signal corresponding to the first signal.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayuki Suzuki
  • Patent number: 11002997
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigo Namioka, Yasutaka Nakashiba
  • Publication number: 20210134818
    Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki KAWASHIMA
  • Patent number: 10997043
    Abstract: A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuo Kato, Hiroshi Morita
  • Patent number: 10998288
    Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 4, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 10998246
    Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of preparing a lead frame in which a plurality of device forming regions are arranged in a matrix, a die bonding step of mounting a semiconductor chip on each device region, a resin sealing step of individually covering each semiconductor chip with a sealing body, and a lead plating step of plating an outer portion of a lead exposed from the sealing body. Between the resin sealing step and the lead plating step, an inspection step for detecting defective products in the resin sealing step and a defective product removal step for removing a device region of defective products are provided.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Noriaki Mineta
  • Patent number: 10997105
    Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Taki, Tadaaki Tanimoto
  • Patent number: 10998432
    Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata