Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.

Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.

Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.

Abstract: A semiconductor device includes: a constant current generating circuit unit; a first current mirror circuit unit having a constant current as an input current and generating a first mirror current as a mirror current; a level shift circuit unit including a clamp transistor between whose drain and source a first mirror current flows and to whose base a power supply voltage of the constant current generating circuit unit is applied, and a transistor that is connected in series to the clamp transistor and through which the first mirror current flows; a second current mirror circuit unit having as an input stage a transistor and having as an output stage a transistor through which a second mirror current replicating the first mirror current flows; and an error absorption circuit unit connected to a terminal for outputting the second mirror current of the output-stage transistor in the second current mirror circuit unit.

Abstract: A video image encoding device includes: an image encoding unit that performs predictive encoding by obtaining a difference between a divided image included in a frame as a target of predictive encoding and a prediction image; local decode generation unit that decodes an encoding result of the divided image by the image encoding unit to generate a reference image; a first buffer that stores pixel data generated by the local decode generation unit; a compression unit that refers to the first buffer to compress the reference image and generates compressed data; an allowable data amount setting unit that presets an allowable data amount to be stored in the memory for each predetermined area of the frame as the target of the predictive encoding; and a reference image storage determination unit that determines whether the compressed data is store in the memory based on the allowable data amount, and stores the compressed data in the memory based on a determination result of storing the compressed data in the memory

Abstract: A stacked-layer body including a gate insulating film and a control gate electrode is formed in a product region and a scribe region. Next, a gate insulating film and a conductive film are so formed that the stacked-layer body is covered. Next, an etching process is so performed to the conductive film that an upper surface of the conductive film is lower than that of an upper surface of the stacked-layer body, thereby forming a measurement pattern in the scribe region. Next, a memory gate electrode is formed by patterning the conductive film in the product region. Next, a silicide layer is formed on an upper surface of the memory gate electrode in the product region in a state where an upper surface of the measurement pattern is covered by an insulating film. Next, a resistance value of the measurement pattern covered by the insulating film is measured.

Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.

Abstract: A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: A data processing device includes a first CPU (Central Processing Unit), a first memory, a CAN (Controller Area Network) controller and a system bus coupled to the first CPU, the first memory and the CAN controller, wherein the CAN controller comprises a receive buffer that stores a plurality of messages each of which has a different ID, and a DMA (Direct Memory Access) controller that selects the latest message among messages having a fist ID stored in the receive buffer and transfers the selected latest message to the first memory, wherein the message is one of CAN, CAN FD and CAN XL messages.

Abstract: A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.

Abstract: In a semiconductor device having MONOS memories configured by fin-type MISFETs, an increase in parasitic capacitance between wirings accompanying miniaturization of the semiconductor device is prevented, and the reliability of the semiconductor device is improved. In a memory cell array in which a plurality of MONOS type memory cells formed on fins are arranged, source regions formed on the plurality of fins arranged in a short direction of the fin are electrically connected to each other by one epitaxial layer straddling the fins.

Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.

Abstract: A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.