Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10718823
    Abstract: A device for open load diagnosis of a signal line in a digital system in which a logic state is represented by a band of voltages lying between first and second voltage limits is described. The device is configured to cause the signal line to reach a first, stable voltage lying in the band, to apply a second, different voltage to the signal line lying in the band and without leaving the band, to perform a time constant dependent measurement so as to determine a value of a parameter which is or depends on resistance of a load between the signal line and a reference line, to compare the value of the parameter with a reference value of the parameter and, in dependence on comparison, to signal the result.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hans-Juergen Braun
  • Patent number: 10720203
    Abstract: A semiconductor device is provided that operates at improved write speeds without an increase in area. The semiconductor device according to the invention includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines provided to each row of the memory cells, a plurality of bit line pairs provided to each column of the memory cells, sense amplifiers that amplify the potential difference in the bit line pairs, data line pairs that transfer data to the bit line pairs, column selection circuits that permit receiving the data from the data line pairs, a column decoder that transmits column selection signals to the column selection circuits, and a sense amplifier control circuit that activates the sense amplifiers after the column decoder transmits the column selection signals to the column selection circuits.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Masahiro Yoshida
  • Patent number: 10714415
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 10712803
    Abstract: To start power supply at a high current without applying USB Power Delivery, a power supply system includes a power supply device having a first USB connector conforming to the USB Type-C standard, and a power receiving device having a second USB connector conforming to the USB Type-C standard. The second USB connector includes a high current notification pin for notifying that it is possible to receive power at a high current greater than a predetermined reference current. When the second USB connector is coupled to the first USB connector, the power receiving device notifies the power supply device of the fact that it is possible to receive power at a high current greater than the predetermined reference current, through the high current notification pin. When receiving the notification, the power supply device determines that it is possible to start power supply to the receiving device at a high current.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satomi Suganuma
  • Patent number: 10714330
    Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 14, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoo Nakayama, Tatsuya Usami
  • Patent number: 10705143
    Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10706902
    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10708064
    Abstract: To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature. A signature verification unit performs signature verification by using the public key and the signature acquired by the acquiring unit, before the program acquired by the acquiring unit is booted. A calculation unit calculates a first MAC value by using a device eigenvalue and stores the first MAC value, when the result of signature verification by the signature verification unit is appropriate. A boot unit calculates a second MAC value by using the device eigenvalue, compares the second MAC value and the stored first MAC value with each other to determine that the program is legitimate, and executes boot based on the determination result.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seishiro Nagano, Shigenori Miyauchi
  • Patent number: 10706178
    Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Sugita, Koji Adachi, Yoichi Yuyama
  • Patent number: 10707894
    Abstract: A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tetsuo Matsui, Mitsuya Fukazawa, Tomohiko Yano
  • Patent number: 10707223
    Abstract: Characteristics of a semiconductor device having a nonvolatile memory are improved. A high dielectric constant film is provided on an insulating film between a memory gate electrode and a fin as components of a nonvolatile memory. The high dielectric constant film is provided over the top of the fin and the top of an element isolation region, but is not provided over a side surface of the fin. In this way, since the high dielectric constant film is provided over the top of the fin and the top of the element isolation region, it is possible to relax an electric field in the vicinity of each of the upper and lower corner portions of the fin, leading to an improvement in disturbance characteristics.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Narumi
  • Patent number: 10707762
    Abstract: An object of the present invention is to provide a power supply voltage stabilizing method that can suppress the performance of switching power supply from being deteriorated even when a battery voltage varies and/or load conditions change. In a power supply voltage stabilizing method of a switching power supply including an output power MOS to which a battery voltage is supplied and a PWM feedback control unit that controls the output power MOS, the PWM feedback control unit includes a voltage feedback controller that controls on the basis of a power supply voltage output from the switching power supply and a current feedback controller that controls on the basis of a current output from the switching power supply. A variation in the battery voltage and/or a change in the load condition of the switching power supply are/is detected, and the bandwidth of the PWM feedback control unit is dynamically changed in accordance with the result of the detection.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayuki Ida
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Publication number: 20200212176
    Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto KOSHIMIZU, Hideki NIWAYAMA, Kazuyuki UMEZU, Hiroki SOEDA, Atsushi TACHIGAMI, Takeshi IIJIMA
  • Patent number: 10700519
    Abstract: A power supply system includes a plurality of voltage sources, a switch circuit that switches between a state in which the plurality of voltage sources are connected in series and a state in which the plurality of voltage sources are connected in parallel, and a voltage control circuit that boosts an input voltage. The switch circuit connects the plurality of voltage sources in series, supplies an output of the plurality of serially connected voltage sources to an output node of the voltage control circuit, thereafter connects the plurality of voltage sources in parallel, and supplies outputs of the plurality of parallel-connected voltage sources to the voltage control circuit, and the voltage control circuit boosts voltages of the plurality of parallel-connected voltage sources.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshifumi Ikenaga
  • Patent number: 10700693
    Abstract: The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akemi Watanabe
  • Patent number: 10692878
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Patent number: 10693396
    Abstract: To surely detect a back electromotive force generated in a non-conduction phase at an extremely low duty ratio, a motor driving system includes a three-phase motor, an inverter circuit, and a semiconductor device. A controller included in the semiconductor device compares a voltage at an output node corresponding to a non-conduction phase of the inverter circuit and a reference voltage with each other, thereby estimating a position of a rotor of the three-phase motor and generating a pulse width modulation signal based on the estimated position of the rotor. The controller detects the voltage at the output node of the non-conduction phase in a regeneration period of the pulse width modulation signal when a duty ratio of the pulse width modulation signal is less than a threshold value, the regeneration period being a period in which current is made to flow to the three-phase motor on a regeneration path.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Patent number: 10693476
    Abstract: Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Maruyama, Noriaki Matsuno
  • Publication number: 20200186748
    Abstract: A photographing control device capable of storing images to be stored at appropriate timings is provided. The analysis result acquiring unit acquires an analysis result of an image obtained by photographing an object by the photographing device. The status acquisition unit acquires a detection result obtained by detecting the status of the object by the sensor. The index determination unit determines the degree of these indexes for each of a plurality of indexes including those relating to the object based on the image analysis result and the detection result of the state of the object. The evaluation value calculation unit calculates an evaluation value for evaluating the stored value of the image using the degree of the index. When the evaluation value exceeds a predetermined threshold value, the image storage control unit 15 controls so as to store an image.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 11, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehito BABA