Patents Assigned to Renesas Technology Corporation
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Patent number: 7795648Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: September 14, 2010Assignee: Renesas Technology CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Publication number: 20100219498Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.Type: ApplicationFiled: August 7, 2009Publication date: September 2, 2010Applicant: RENESAS TECHNOLOGY CORPORATIONInventor: Shu SHIMIZU
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Patent number: 7781846Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: GrantFiled: January 5, 2009Date of Patent: August 24, 2010Assignee: Renesas Technology CorporationInventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Patent number: 7773426Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.Type: GrantFiled: May 23, 2008Date of Patent: August 10, 2010Assignee: Renesas Technology CorporationInventors: Ken Matsubara, Yoshinori Takase, Tomoyuki Fujisawa
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Patent number: 7773662Abstract: Synchronization techniques for reducing the effects of time dispersive wireless communications channels are presented. A synchronization technique for communications over a time dispersive wireless channel includes receiving a signal having at least identical first and second symbols, and calculating a metric for each sampling time by correlating respective samples of the first symbol included in a first sampling window with respective samples of the second symbol included in a second sampling window. The technique further includes identifying one of the sampling times at which the metric attains a maximum value, and estimating an optimal time offset for synchronizing to the received signal based on the identified sampling time. Optionally, the technique further includes estimating a carrier frequency offset based on the difference of phase of the complex conjugate samples at the maximum absolute value of the metric.Type: GrantFiled: March 8, 2006Date of Patent: August 10, 2010Assignee: Renesas Technology CorporationInventors: Yves-Paul Nakache, Nikolaus Lehmann
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Patent number: 7769074Abstract: Methods and systems for detecting and synchronizing to frequency hopped packets are presented. A technique for detecting a transmitter frequency hopping pattern includes receiving a packet of preamble symbols respectively transmitted over multiple frequency sub-bands according to the transmitter frequency hopping pattern, and partitioning predetermined frequency hopping patterns into disjoint groups of patterns, each group of patterns having an associated periodicity of the received preamble symbols. A group of patterns is selected by comparing a correlation metric of two received preamble symbols for each of the associated periodicities in a first selected frequency sub-band, and a pattern from the selected group of patterns is selected based on a timing of a detected first peak of the correlation metric in a second selected frequency sub-band.Type: GrantFiled: March 8, 2006Date of Patent: August 3, 2010Assignee: Renesas Technology CorporationInventors: Yves-Paul Nakache, Nikolaus Lehmann
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Patent number: 7765269Abstract: This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.Type: GrantFiled: November 4, 2004Date of Patent: July 27, 2010Assignee: Renesas Technology CorporationInventors: Nobuyasu Kanekawa, Hiromichi Yamada, Kohei Sakurai, Kotaro Shimamura, Yuichiro Morita, Satoshi Tanaka
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Publication number: 20100155960Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: Renesas Technology CorporationInventors: Teruaki KANZAKI, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 7741656Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.Type: GrantFiled: December 22, 2009Date of Patent: June 22, 2010Assignees: Renesas Technology Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
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Patent number: 7737023Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: August 19, 2008Date of Patent: June 15, 2010Assignee: Renesas Technology CorporationInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Patent number: 7718526Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: GrantFiled: July 16, 2007Date of Patent: May 18, 2010Assignee: Renesas Technology CorporationInventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 7687914Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.Type: GrantFiled: October 30, 2007Date of Patent: March 30, 2010Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
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Publication number: 20100072551Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: ApplicationFiled: November 25, 2009Publication date: March 25, 2010Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7681308Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: GrantFiled: May 9, 2008Date of Patent: March 23, 2010Assignees: Renesas Eastern Japan Semiconductor, Inc., Renesas Technology CorporationInventors: Bunshi Kuratomi, Fukumi Shimizu
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Patent number: 7671381Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.Type: GrantFiled: December 22, 2008Date of Patent: March 2, 2010Assignees: Renesas Eastern Japan Semiconductor, Inc., Renesas Technology CorporationInventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
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Patent number: 7655993Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.Type: GrantFiled: April 23, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology CorporationInventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
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Publication number: 20100011191Abstract: A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the normative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not.Type: ApplicationFiled: September 22, 2009Publication date: January 14, 2010Applicant: RENESAS TECHNOLOGY CORPORATIONInventor: Toyohiko YOSHIDA
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Patent number: 7645655Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: June 5, 2006Date of Patent: January 12, 2010Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7643042Abstract: A display driver for outputting gradation voltages corresponding to gradation data from an external device to pixels. The display driver includes a generator for generating a plurality of gradation voltages having a plurality of levels based on a reference voltage, and a selector for selecting at least one gradation voltage corresponding to the gradation data from the plurality of gradation voltages generated by the generator. The gradation data includes multi-bits for each color of red, green and blue, and the generator outputs or stops outputting each gradation voltage according to data for color reduction from the external device. The generator stops outputting at least one gradation voltage that is unnecessary for displaying as a result of the color reduction, when the color of the gradation data is reduced according to the data for color reduction.Type: GrantFiled: April 20, 2005Date of Patent: January 5, 2010Assignee: Renesas Technology CorporationInventors: Yasuyuki Kudo, Akihito Akai, Kazuo Okado, Toshimitsu Matsudo, Atsuhiro Higa
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Patent number: RE41245Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.Type: GrantFiled: June 9, 2005Date of Patent: April 20, 2010Assignee: Renesas Technology CorporationInventors: Ryu Makabe, Masaki Tsukude, Hirotoshi Sato, Shinichi Kobayashi