Patents Assigned to Renesas Technology Corporation
  • Patent number: 7323771
    Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Ryo Fujita, Osamu Kubo, Kouki Noguchi, Masaharu Kubo, Michihiro Mishima, Yasuhiko Takahashi
  • Patent number: 7322531
    Abstract: A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: January 29, 2008
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corporation
    Inventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
  • Patent number: 7324787
    Abstract: In a radio communication system having a phase control loop for phase modulation and an amplitude control loop for amplitude modulation and being capable of time divisional transmission and reception under a predetermined time management, when transmission in a first mode is switched to transmission in a second mode or when transmission in the second mode is switched to transmission in the first mode, the output level of the power amplifier is lowered once to a predetermined level higher than the level when transmission related circuits are activated, and thereafter the output level of the power amplifier is again ramped after the settings have been changed but without starting of a transmission oscillator, establishing of the phase control loop and the amplitude control loop.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: January 29, 2008
    Assignees: Renesas Technology Corporation, TTPCOM Limited
    Inventors: Noriyuki Kurakami, Kazuhiko Hikasa, Ryoichi Takano, Patrick Wurm
  • Patent number: 7321252
    Abstract: In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 22, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori
  • Patent number: 7315153
    Abstract: A switching power supply circuit in which a series circuit comprising a resistive element and a capacitive element is provided in a parallel configuration with an inductor which supplies a load current to a load circuit, a voltage comparator having first and second threshold voltages discriminates a voltage obtained from a mutual connecting point of the series circuit therefrom and controls a switch element for supplying a current to the inductor, thereby varying the current supplied to the inductor in accordance with a variation in the load current is combined with a series power supply circuit which shares the load current of the load circuit.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: January 1, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Tomohiro Tazawa, Shinichi Yoshida
  • Patent number: 7304539
    Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: December 4, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Hirokazu Tsurumaki, Hiroyuki Nagai, Tomio Furuya, Makoto Ishikawa
  • Patent number: 7292496
    Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: November 6, 2007
    Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
  • Patent number: 7286074
    Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Junya Kudoh, Kouichi Yahagi, Tatsuji Matsuura
  • Patent number: 7286397
    Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Hitoshi Miwa, Hiroaki Kotani
  • Patent number: 7283719
    Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: October 16, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Masataka Okayama, Tomohisa Kohiyama, Nobukazu Kondo, Kazutoshi Katoh, Kazuaki Tanaka, Yoshihiro Harada
  • Patent number: 7280426
    Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Seiji Miura, Kazushige Ayukawa
  • Patent number: 7280308
    Abstract: The Invention provides a motor drive semiconductor integrated circuit for driving and controlling a voice coil motor that can conduct a seek operation, a track follow operation and a settling operation through PWM control, has desired control accuracy and can be produced by a CMOS process. In a voice coil motor drive circuit (200) for executing positioning control of a magnetic head by feedback-controlling a driving current of a voice coil motor (108) for moving a magnetic head (106) over a magnetic disk for reading information from a storage track on the magnetic disk driven for rotation while a read state of the magnetic head is being monitored, head movement control such as a seek operation, a track follow operation etc, of the magnetic head is executed by PWM driving on the basis of a command value from a controller.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corporation
    Inventor: Yasuhiko Kokami
  • Patent number: 7277979
    Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: October 2, 2007
    Assignees: Renesas Technology Corporation, Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Naoki Yada, Eiichi Ishikawa
  • Patent number: 7271662
    Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Hitoshi Akamine, Masahiro Tsuchiya, Kyoichi Takahashi, Kazuhiro Koshio
  • Patent number: 7268611
    Abstract: A semiconductor device capable of achieving downsizing without reducing the power supply efficiency and capable of reducing switching noises and a memory card using the same are disclosed. The device comprises a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit for controlling an output voltage at a nearby location of the final stage, and one or more internal elements to which the final output voltage is supplied. A primary voltage booster circuit at the first stage includes an inductance element, a switching element, a diode and a driver circuit. At a metal core part of the inductance element, a metal wiring line is used, which was formed by use of a fabrication process of semiconductor integrated circuits, while employing for its core part an inter-wiring layer dielectric film that was formed using the fabrication process.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Mutsumi Kikuchi, Noboru Akiyama, Hiroyuki Shoji, Fumio Murabayashi, Akihiko Kanouda, Takashi Sase, Koji Tateno
  • Publication number: 20070202692
    Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 30, 2007
    Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATION
    Inventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
  • Patent number: D552098
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 2, 2007
    Assignees: Renesas Technology Corporation, Sony Kabushiki Kaisha
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama, Takashi Totsuka, Yoshitaka Aoki, Keiichi Tsutsui
  • Patent number: D552099
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 2, 2007
    Assignees: Renesas Technology Corporation, Sony Kabushiki Kaisha
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama, Takashi Totsuka, Yoshitaka Aoki, Keiichi Tsutsui
  • Patent number: D552612
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama, Takashi Totsuka
  • Patent number: D556764
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: December 4, 2007
    Assignees: Renesas Technology Corporation, Sony Kabushiki Kaisha
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama, Takashi Totsuka, Yoshitaka Aoki, Keiichi Tsutsui