Abstract: A method of communicating information in a communication network with a plurality of hierarchically addressed nodes includes receiving communication packets identifying 1-hop neighbor node addresses, a number of on-tree neighbors of neighbor nodes transmitting the received packets, and forwarding node addresses of forwarding nodes from which information in the received packets are to be rebroadcast. Further, the method includes identifying each 1-hop neighbor node which should be a forwarding node based on stored addresses and numbers of on-tree neighbors, and producing and transmitting a rebroadcast packet including addresses of forwarding nodes. A communication network system, a communication node in a communication network, and a computer program product include similar features. Communication packets embodied in an electromagnetic wave includes an address, a number of on-tree neighbors of neighbor nodes, and forwarding nodes from which the packets are to be rebroadcast.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract: A plasma treatment apparatus has a reaction vessel (11) provided with a top electrode (13) and a bottom electrode (14), and the first electrode is supplied with a VHF band high frequency power from a VHF band high frequency power source (32), while the bottom electrode on which a substrate (12) is loaded and is moved by a vertical movement mechanism. The plasma treatment system has a controller (36) which, at the time of a cleaning process after forming a film on the substrate (12), controls a vertical movement mechanism to move the bottom electrode to narrow the gap between the top electrode and bottom electrode and form a narrow space and starts cleaning by a predetermined high density plasma in that narrow space. In the cleaning process, step cleaning is performed. Due to this, the efficiency of utilization of the cleaning gas is increased, the amount of exhaust gas is cut, and the cleaning speed is raised. Further, the amount of the process gas used is cut and the process cost is reduced.

Abstract: A multiple carrier wireless communications system includes a channel predictor, a performance predictor, and a link adapter. The channel predictor is configured to predict channel state information for a next packet based on channel state information for the current packet. The performance predictor includes an uncoded performance predictor configured to predict system performance at an input of a decoder based on a modulation type and the predicted channel state information for the next packet, and a decoder input-output performance mapper configured to determine a required coding rate based on a requested system performance and the predicted system performance at the input of the decoder. The link adapter includes a modulation and coding scheme (MCS) updater configured to identify a MCS based on the required coding rate.

Abstract: A multiple carrier wireless communications system includes a channel predictor, a performance predictor, and a link adapter. The channel predictor predicts channel state information for a next packet based on channel state information for the current packet. The performance predictor includes an uncoded performance predictor to predict system performance at a decoder input based on a modulation type and the predicted channel state information for the next packet, and a decoder input-output performance mapper to predict system performance at a decoder output based on a coding rate and the predicted system performance at the decoder input. The link adapter includes a link throughput controller to generate a throughput indicator based on a requested system performance and the predicted system performance at the decoder output, and a modulation and coding scheme (MCS) updater to identify a MCS based on the throughput indicator.

Abstract: The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

Abstract: There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.

Abstract: A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract: There are provided a transmission/reception switching circuit which is small in insertion loss and harmonic distortion and allows an increase in the output power of a power amplifier and an electronic component for communication on which the transmission/reception switching circuit is mounted. As an element composing a transmission/reception switching circuit in a wireless communication system, series-connected FETs or a multi-gate FET are used in place of a diode. Gate resistors connected between the individual gate terminals and a control terminal are designed to have resistance values which become progressively smaller from the gate to which a highest voltage is applied toward the gate to which a lowest voltage is applied.

Abstract: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.

Abstract: A method of inspecting a specimen, including: emitting a light from a lamp of a light source; illuminating a specimen on which plural patterns are formed with the light emitted from the light source and, passed through an objective lens; forming an optical image of the specimen by collecting light reflected from the specimen by the illuminating and passed through the objective lens and a image forming lens; detecting the optical image with a TDI image sensor; and processing a signal outputted from the TDI image sensor and detecting a defect of a pattern among the plural patterns formed on the specimen, wherein the image detected by the TDI image sensor is formed with light having a wavelength selected from the wavelengths of the light emitted from the light source.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.