Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: The present invention relates to detection of defects with simple specification of the coordinates, in the inspection of an object having a plurality of patterns in which a portion having the two-dimensional repetition and portions having the repetition only in the X direction and in the Y direction are mixedly present. The cross comparison between a notice point and comparison points, for example which are repetitive pitches away from the notice point, is carried out, and only the portion having the difference which can be found out with any of the comparison points is extracted as a defect candidate, which results in that the portion having the two-dimensional repetition as well as the portion having the repetition only in the X direction or in the Y direction can be inspected.

Abstract: A receiving circuit of a direct conversion system is provided which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to thereby perform frequency conversion, and a high gain amplifier circuit in which a plurality of programmable gain amplifiers and a plurality of filters which eliminate noise of the received signal and an unnecessary wave, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to thereby allow execution of a DC offset cancel operation of the corresponding programmable gain amplifier on the pre-stage side of the high gain amplifier circuit.

Abstract: The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, including a step of loading a first part of the unaligned data into a first storage location and rotating the first part from a first position to a second position in the first memory location. Next a second part of the unaligned data is loaded into a second storage location and rotated from one position to another position. Then the first storage location is combined with the second storage location using a logical operation into a result storage location. The storage locations may be, for example, 64-bit registers. The logical operation may be a bit-wise OR operation.

Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.

Abstract: On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a fuse region provided with a plurality of fuses is provided. The reflector layer of copper has a plane of reflection recessed downward to reflect a laser beam. The reflector layer of copper is arranged to overlap substantially the entirety of the fuse region, as seen in a plane. A laser beam radiated to blow the fuse can have a reduced effect on a vicinity of the fuse region. A semiconductor device reduced in size can be obtained.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A communication semiconductor integrated circuit device is capable of transmission in two or more different modulation modes and outputting transmission signals with less distortion. The communication semiconductor integrated circuit device comprises a gain variable amplification circuit which amplifies I-signals and Q-signals; and a mixer circuit which synthesizes the amplified I-signals and Q-signals and local oscillation signals to carry out modulation and frequency conversion. The communication semiconductor integrated circuit device is capable of transmission in two or more different modulation methods, for example, in GSM mode and EDGE mode. A low-pass filter of second or higher order is placed between the gain variable amplification circuit and the mixer circuit.

Abstract: Because there are different voltages at two current output terminals of a current divider, the voltages at the current input terminals of two current switch circuits are not affected mutually even with a large amplitude of local signals. Accordingly, the performance of a quadrature mixer can be enhanced by increasing the amplitude of the local signals. Bias currents are supplied to the two current switch circuits through the current divider from a common DC current source which essentially supplies a bias current to a V/I converter and, therefore, power consumption is reduced.

Abstract: To calibrate the VGA of a read head, test signals from a DAC are input to the VGA and the output of the VGA is observed, with the gain of the VGA being adjusted as appropriate. So that the DAC need not be made with tight tolerances, a DC signal can be fed into the DAC prior to VGA calibration, and an auxiliary ADC is used to receive the output of the DAC and to determine, for a given DC input, what the signal produced by the DAC actually is. In this way, during subsequent VGA calibration the test signal from the DAC is known not by virtue of the DAC having a tight manufacturing tolerance but by virtue of the actual measurements of its outputs for given register inputs.

Abstract: An object of the present invention is to provide a radio frequency power amplifier of multi stage amplifying method that is designed to reduce instability of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby operate stably. Another object of the present invention is to provide a radio frequency power amplifier that is designed to reduce distortion of output power caused by electromagnetic coupling of bias supply terminals and interconnections of each stage to thereby provide high efficiency.

Abstract: A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.

Abstract: Providing a wireless communication device that, even if clock stop of a radio frequency part is controlled by a baseband part operating on the same clock signal, can resume clock oscillation, and makes it easy to time the clock reactivation to other operations based on a shared clock. The wireless communication device comprises an RF part generating a first clock signal and a baseband part. The baseband part generates a second clock signal, controls the generation and stop of the first clock signal, uses the first clock signal to perform data processing and a clocking operation, and in a low power consumption state in which the first clock signal is stopped, uses the second clock signal to perform a timer operation and a clocking operation. The generation timing of the first clock signal can be generated by the timer operation using the second clock signal.

Abstract: In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the object of the present invention is to provide a technology of allowing a nonvolatile semiconductor memory to increase the capacity without increasing the power supply circuits which are the peripheral circuits of the nonvolatile semiconductor memory.

Abstract: An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Abstract: A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.

Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.

Abstract: By flexibly coping with both image sensors of a CCD sensor and a CMOS sensor without providing any external circuit, a signal processing is performed. In a sensor selecting switch provided in an image-sensor signal-processing circuit, first and fourth switches are turned on when the CMOS sensor is connected, and second and third switches are turned on when the CCD sensor is connected. The sensor selecting switch is controlled by a control signal generated in a control circuit, based on sensor selection data which is stored in a register and which is data for selecting the CCD or CMOS sensor. By so doing, even if polarity of an output signal of the image sensor is reversed, a normal signal is inputted to both inputs of the CDS amplifier, whereby it is possible to flexibly cope with both of the CCD and CMOS sensors.

Abstract: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.