Abstract: SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at predetermined flow rates, and SiGe:C is formed by an epitaxial growth technique. By diluting the SiH3CH3, the concentration of oxygen-based impurity contained in the SiH3CH3 is reduced and hence, the oxygen-based impurity which is supplied to a chamber are reduced whereby the concentration of oxygen-based impurity contained in the SiGe:C formed in a film is reduced.

Abstract: A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained.

Abstract: A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between the second magnetic layer and the first fixed layer, a first drive circuit passing a write current through a first write current line in a data write operation, and thereby generating a data write magnetic field acting on magnetization of the free layer, and a second drive circuit passing a spin injection current between the first magnetic layer and the first fixed layer in a data write operation, and thereby exerting a force in the same direction as or in the direction opposite to the magnetization direction of the first fixed layer on the magnetization of the free layer.

Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.

Abstract: When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.

Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.

Abstract: A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period ?). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period ?).

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

Abstract: In a SPDT switch, a resistor for leak path is connected between a terminal for antenna and a reference potential. The resistor for leak path allows charge capacitances accumulated in electrostatic capacitor elements provided as DC cut capacitors connected to transmission signal terminals and reception signal terminals to be discharged and allows rapid lowering of a potential at the terminal for antenna. In the SPDT switch, a switching characteristic is improved and a delay in the rising edge of a low-power slot which comes after a high-power slot is reduced.

Abstract: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.

Abstract: Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.

Abstract: A memory card has: a flash memory chip for storing digital certificates and a seed of random numbers; a controller chip which can execute a managing process for managing the digital certificates and a random number generating process for generating the pseudo random numbers by using the seed of random numbers; and an IC card chip which can execute an authenticating process for authenticating personal identification information (PIN) inputted from a host apparatus and an encrypting process for encrypting the seed of random numbers. Thus, a processing time of security processes is reduced while assuring safety of the security processes.

Abstract: In order to offer the technology which can form the pattern of the antenna of the inlet for electronic tags accurately and cheaply, the resist layer at the time of forming the pattern of an antenna by chemical etching is formed using a photogravure printing machine. Let the extending direction of region 16C which has the minimum width in the height of the front surface of a gravure plate be an opposite direction to the direction of rotation of a gravure plate (a doctor's relative direction of movement seen from the gravure plate). The radius of curvature of an inner circumference of the curved part in region 16B is made larger than the radius of curvature of a periphery. The outer edge of region 16D is formed so that it may become forward tapered shape-like toward position D, so that the width of region 16D may become larger than the width of region 16C in position D which the end of height attains.

Abstract: To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.