Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.

Abstract: A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. Thus, a time period till the cutoff of the power source is easily made comparatively long. The power source feeding terminals should preferably be extended onto the insertion side of the semiconductor device, but an extendible distance is sometimes liable to be limited.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: There is provided a semiconductor device capable of supplying an analog input signal higher than or equal to an operating power supply voltage. An electrostatic discharge protection circuit corresponding to the analog input signal is provided for an external terminal that is supplied with an analog input signal generated with a first power supply voltage. A voltage divider resistor divides the analog input signal passing through the electrostatic discharge protection circuit into a voltage corresponding to a second power supply voltage lower that the first power supply voltage. An input circuit operating on the second power supply voltage receives the analog input signal divided by the voltage divider resistor to form an internal analog signal. There are provided first and second unidirectional elements. The first unidirectional element passes current from the input circuit's input terminal to the second power supply voltage.

Abstract: An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes.

Abstract: A display driver for outputting gradation voltages corresponding to gradation data from an external device to pixels. The display driver includes a generator for generating a plurality of gradation voltages having a plurality of levels based on a reference voltage, and a selector for selecting at least one gradation voltage corresponding to the gradation data from the plurality of gradation voltages generated by the generator. The gradation data includes multi-bits for each color of red, green and blue, and the generator outputs or stops outputting each gradation voltage according to data for color reduction from the external device. The generator stops outputting at least one gradation voltage that is unnecessary for displaying as a result of the color reduction, when the color of the gradation data is reduced according to the data for color reduction.

Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.

Abstract: Semiconductor devices are provided with high performance high-frequency circuits in which interference caused by inductors is reduced. In a semiconductor device including a modulator circuit to modulate a carrier wave by a base band signal to output an RF signal and a demodulator circuit to demodulate the RF signal by use of the carrier wave to gain the base band signal and a local oscillator to generate the carrier wave, inductors respectively having a closed loop wire are adopted. Interference caused by mutual inductance is reduced by the closed loop wire. For example, where inductors are adopted in the modulator circuit, a closed loop wire is disposed around the outer periphery of the inductors.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

Abstract: A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion

Abstract: A semiconductor integrated circuit device comprises: a circuit block, a first MOS transistor, a first power line, a second power line, a third power line, and a drive circuit. The first MOS transistor is connected between the first and second power lines. The circuit block is connected between the second and third power lines. The drive circuit controls a voltage supplied to a gate of the first MOS transistor. The first MOS transistor is off in a standby state and on in an operation state. During a shift from the standby state to the operation state and a shift from the operation state to the standby state, the drive circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate.

Abstract: The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

Abstract: The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space is designed considering a thickness of a cutting edge of a blade and relative positioning error, and the blade does not cross any metal wirings when the blade passes through the dicing area, thereby preventing the generation of an abruption or a burr due to the dicing to enhance a yield in IC production.

Abstract: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region.

Abstract: A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.

Abstract: Size of a chipping is made small, suppressing blinding of a blade, when performing dicing of a wafer. When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Z2 from a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose point is V character form. By processing it in this way, cutting resistance goes up and blinding of a blade can be prevented. Hereby, the size of a chipping can be suppressed small, preventing blinding of a blade.