Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

Abstract: Methods and systems for operating a multiphase voltage regulator are described. The multiphase voltage regulator can include a plurality of power stages. A controller can be connected to the plurality of power stages. The controller can detect a number of activated power stages among the plurality of power stages. The controller can adjust a gain of a current sense feedback loop of the controller to control a load-transient response of the multiphase voltage regulator. The adjustment to the gain can be based on the number of activated power stages.

Abstract: Systems, devices, and methods for isolating digital signals are described. A carrier signal can be modulated using a first signal to generate a first modulated signal. The carrier signal and the first modulated signal can be transmitted through a forward path in an isolation barrier, where transmitting the carrier signal through the isolation barrier can transform the carrier signal into a delayed carrier signal. The first modulated signal can be demodulated to recover the first signal. The delayed carrier signal can be modulated using a second signal to generate a second modulated signal. The delayed carrier signal and the second modulated signal can be transmitted through a return path in the isolation barrier, where the return path and the forward path has opposite directions.

Abstract: A system and method for authenticating sound verbalized or otherwise generated by a live source within a monitored setting for voice-controlled or sound-controlled automation of a responsive process. One or more classifiers each generate a decision value according to values of predetermined signal features extracted from a received digital stream, and a sound type classification is computed according to an aggregate score of a predetermined number of decision values. The actuation of the responsive process is authenticated when the system discriminately indicates the captured sound signals to be verbalized or generated by a live source. The responsive process is thereby suppressed when the sound is instead determined to be reproduced or otherwise previously transduced, for example by a transmission or recording.

Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

Abstract: An inductive position sensor including at least one transmit coil, an absolute position receive coil pair, a high-resolution position receive coil pair and a conductive moving target, the absolute position receive coil pair and the high-resolution receive coil pair together define a measurement area of the inductive position sensor and the moving target can move in this measurement area, the absolute position coil pair has a first sine receive coil and a first cosine receive coil, both having one period over the measurement area of the inductive position sensor, the high-resolution position receive coil pair has a second sine receive coil and a second cosine receive coil, both having at least two periods over the measurement area of the inductive position sensor, the absolute position receive coil pair and the high-resolution position receive coil pair are arranged in the same area of a printed-circuit board of the inductive position sensor.

Abstract: An authentication method for authenticating a wireless power transmitter to a wireless power receiver includes receiving a SSP value, an ID, and a random number RND from a wireless power receiver; determining an index based on the RND; choosing a base code from a set of base codes according to the index; determining a secure code from the base code, the index, the RND, the SSP value, and the ID; and transmitting the secure code to the wireless power receiver. A further method includes receiving a secure code from the wireless power transmitter; retrieving an index from the secure code; determining a base code from a set of base codes according to the index; calculating a second secure code; and authenticating the wireless power transmitter by comparing the secure code and the second secure code.

Abstract: A driver circuit for providing a driver current for operating a light emitting unit at a brightness level corresponding to a value of a brightness code. The driver circuit includes a digital-to-analog converter, DAC, stage configured to generate an intermediate signal in dependence of the value of the brightness code. Furthermore, the driver circuit includes a gain stage configured to amplify the intermediate signal in dependence of the value of the brightness code to provide the driver current.

Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: A driver for use with a light source is presented. The driver includes a first circuit and a second circuit. The first circuit is adapted to control an amount of current flowing through the light source to switch the light source between a first state when the light source is on and a second state when the light source is off. The second circuit is adapted to generate a leak current so that during the second state the leak current flows through the light source.

Abstract: A circuit and corresponding method for determining a delay are presented. The circuit includes a delay circuit, a feedback circuit and a controller. The delay circuit receives an input signal having an input edge and provides an output signal having an output edge. The input edge and the output edge are separated by a delay. The feedback circuit causes the delay circuit to generate a series of consecutive output pulses. The controller sets the delay to a first delay value and measures a first period of output pulses; sets the delay to a second delay value and measure a second period of output pulses. The controller then calculates the delay based on a difference between the first period and the second period.

Abstract: Apparatuses, systems and methods for operating a power amplifier are described. A controller can drive a power amplifier chain with first input bias voltages to operate the power amplifier chain in a first operation mode that implements a Doherty amplifier. The controller can drive the power amplifier chain with second input bias voltages to operate the power amplifier chain in a second operation mode that implements a balanced amplifier. The controller can tune the termination circuit in accordance with an operation mode of the power amplifier chain.

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Abstract: In an embodiment, a semiconductor device is disclosed that includes a wired input/output, a wireless input/output, and a battery. A wired charging path between the wired input/output and the battery includes a first transistor and a second transistor. A wireless charging path between the wireless input/output and the battery includes a third transistor and the second transistor.

Abstract: A driver stage configured to switch an output node between a high-side potential and a low-side potential. The driver stage includes a high-side switch arranged between the high-side potential and the output node, a low-side switch arranged between the output node and the low-side potential, and an intermediate circuit arranged between the output node and an intermediate potential, wherein the intermediate potential lies between the high-side potential and the low-side potential. Furthermore, the driver stage includes a control unit configured to operate the driver stage at least in a high-side phase, in a low-side phase and in an intermediate phase.

Abstract: A filter circuit for use with a system configured to be coupled with an electrical load, the filter circuit comprising a first filter, wherein the first filter is configured to receive a first voltage and provide an output voltage, the output voltage being the first voltage after filtering by the first filter, and the filter circuit is configured to adjust the bandwidth of the first filter in response to a load transient.

Abstract: A low dropout regulator for providing an output voltage, the low dropout regulator comprising a resistive device configured to contribute to the stability of the low dropout regulator during operation and to have a resistance that is dependent on a load current.

Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.

Abstract: Described herein is a power converter operable in a pulse frequency modulation (PFM) mode. The power converted may be configured for maintaining a PFM frequency above a predetermined frequency threshold when a load current at an output node of the power converter decreases. The power converter may comprise an inductor. The power converter may be configured to, in a PFM switching cycle: during a positive charge phase of the PFM switching cycle, generate a positive charge across the inductor; and during a negative charge phase of the PFM switching cycle, generate a negative charge across the inductor smaller than or equal to the positive charge, such that a total net charge transferred to the output node during the PFM switching cycle is reduced, so as to maintain the PFM frequency above the predetermined frequency threshold.