Abstract: A semiconductor device includes: an arithmetic circuit that repeats an operation related to a cryptographic processing for the predetermined number of rounds; a holding circuit that holds data related to the number of rounds of an operation of the arithmetic circuit; a judgement circuit that determines whether the number of rounds is the predetermined number of rounds; and an output buffer circuit that outputs the arithmetic result data of the arithmetic circuit when the judgement circuit determines that the number of rounds is the predetermined number. It is configured to duplicate the holding circuit, and not to output the arithmetic result data when two outputs of the duplicated holding circuit are not matched.

Abstract: A transmitter of an RFID communication system to transmit an amplitude modulated transmitter data signal in resonance in an RF-Field over the air and to receive a modulated receiver data signal, which transmitter comprises: a transmitter stage to generate the amplitude modulated transmitter data signal with a particular frequency and waveform based on a carrier signal generated by a carrier signal stage; an antenna connected to the transmitter stage via a matching circuit to transmit the amplitude modulated transmitter data signal in resonance in the RF-Field over the air; a receiver stage connected via the matching circuit to the antenna to receive the modulated receiver data signal; wherein the transmitter furthermore comprises a wave shape measurement stage to measure the shape of the received modulated receiver data signal with equivalent time sampling.

Abstract: A transmitter configured to transmit a modulated transmitter data signal in an RF-Field over the air and configured to receive a modulated receiver data signal, which transmitter comprises a transmitter stage configured to generate the modulated transmitter data signal with a particular frequency and waveform based on a carrier signal and an antenna connected to the transmitter stage via a matching circuit of the transmitter and configured to transmit the modulated transmitter data signal in the RF-Field over the air a receiver stage connected via the matching circuit to the antenna and configured to receive the modulated receiver data signal, wherein the transmitter includes a measurement stage to measure an actual resonance frequency (fpeak) of the antenna and its matching circuit connected to the transmitter stage and to the receiver stage.

Abstract: A DC-DC converter is disclosed. The DC-DC converter includes a first switching element between an external input terminal and an inductor of a smoothing filter, a second switching element provided between the inductor and a reference voltage terminal, a control circuit for on-off controlling the first and second switching elements according to the upper and lower limit values of the output voltage, and a period determination circuit configured to determine the predetermined period based on the voltage corresponding to the upper limit value of the output voltage.

Abstract: A semiconductor device includes a transmission device and a reception device generating a demodulating signal by receiving the transmission signal via the measuring object from the antenna, and performing a processing to the demodulating signal. The transmission device is configured to start modulation at a first phase. The reception device stores a first phase and a physical quantity corresponding to a phase change amount in advance, estimate modulating signal start timing at which the reception signal switches from a non-modulation period to a modulation period based on a waveform of the demodulating signal; calculate a second phase that is a phase at the modulation start timing, calculates a variation to the second phase based on the stored first phase; and determine a physical quantity corresponding to the variation based on the physical quantity corresponding to a stored phase change amount.

Abstract: A system of a power device and a portable device for wireless charging of a battery of the portable device, which power device comprises a first antenna to emit a magnetic field and which portable device comprises a portable antenna exposed to the magnetic field and connected to a charge stage to rectify an antenna signal from the portable antenna and to provide a charge voltage (UI) to charge the battery wherein the power device comprises a second antenna realized identical as the first antenna and arranged in a distance (L) to the first antenna and on the same coil axis (A) as the first antenna to generate a Helmholtz magnetic field and wherein a first power amplifier directly connected to the first antenna and a second power amplifier directly connected to the second antenna are realized identical and on the same substrate.

Abstract: A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.

Abstract: A method for manufacturing a semiconductor device comprising (a) preparing a semiconductor substrate, (b) forming semiconductor elements on the semiconductor substrate, (c) forming an interlayer insulating film on the semiconductor substrate so as to cover the semiconductor elements, (d) forming a first implantation layer in the interlayer insulating film by performing a first ion-implantation, (e) forming a contact hole in the interlayer insulating film, (f) forming a conductive film on the interlayer insulating film so as to fill in the contact hole, (g) removing the conductive film located outside the contact hole by a polishing so that the conductive film inside the contact hole remains. In the (g) step, the polishing is also performed on the interlayer insulating film. And during the polishing, a polishing rate of the first implantation layer is different from a polishing rate of the interlayer insulating film other than the first implantation layer.

Abstract: Systems and methods for a voltage converter are described. A controller can include determining a pulse width modulation (PWM) on time duration being used for operating a voltage regulator. The controller can determine a switching frequency being used for operating the voltage regulator. The controller can determine whether the PWM on time duration is greater than or less than an on time reference. The controller can, in response to determining that the PWM on time duration is less than the on time reference, increase a voltage window for a PWM signal being used to operate the voltage regulator. The controller can, in response to determining that the PWM on time duration is greater than the on time reference, perform a frequency locked loop (FLL) to regulate the switching frequency.

Abstract: A voltage regulator feedback circuit includes a first comparator, a second comparator and a logic circuit. The first comparator is configured to generate an overshoot signal based on a comparison of a voltage regulation target signal to a feedback voltage signal. The second comparator is configured to generate a forward current signal based on a comparison of the current sense amplifier voltage to a reference voltage. The logic circuit is configured to generate a breaking signal based on the overshoot signal and the forward current signal. A gate signal of a transistor connected between a second end of the inductor and a reference ground is generated based at least in part on the breaking signal and is configured to cause the transistor to open based at least in part on the breaking signal having a true value.

Abstract: System and methods for a power converter are described. A controller can generate first clock signals and generate pulse width modulation (PWM) signals using the first clock signals to operate a first number of active phases in a power converter to supply power to a load. The controller can determine the load demands a second number, greater than the first number, of active phases to supply the power. The controller can generate pulse signals and combine the pulse signals with the first clock signals to generate second clock signals having a higher frequency than the first clock signals. The controller can generate the PWM signals using the second clock signals to operate the second number of active phases in the power converter to supply power to the load.

Abstract: An overvoltage protection circuit is provided. The overvoltage protection circuit includes: a current output circuit including a first transistor arranged between a power supply and a CC terminal and a second transistor arranged between the first transistor and the CC terminal, the current output circuit outputting the current to the first transistor to be driven such that a current flows from the power supply; and a gate input circuit controlling a voltage of a gate and a voltage of a back gate of the second transistor, the gate input circuit controls the voltage of the gate and the voltage of the back gate of the second transistor in response to a voltage applied to the CC terminal, and the current output circuit protects the first transistor from the voltage applied to the CC terminal under control of the second transistor.

Abstract: Systems and methods for over current protection are described. A controller can receive a differential feedback voltage signal from a power stage. The differential feedback voltage signal can be proportional to an inductor current through an inductor in the power stage. The controller can amplify the differential feedback voltage signal to generate a differential threshold that includes an upper bound and a lower bound. The controller can compare the amplified differential feedback voltage signal with the differential threshold. The controller can, based on a result of the comparison of the amplified differential feedback voltage signal with the differential threshold, determine whether to adjust at least one of a modulator on-time and a modulator off-time of a control signal to limit the inductor current, wherein the control signal is for driving the power stage.

Abstract: Systems and methods for power converters are described. A digital to analog converter (DAC) can be configured to receive a digital representation of a maximum current value of a power conversion system. The DAC can be further configured to convert the digital representation of the maximum current value into an analog current signal. An analog to digital converter (ADC) can be configured to generate, based on the analog current signal, a digital signal representing a sensed current of the power conversion system as a function of the maximum current value.

Abstract: Systems and methods for a cycle-by-cycle current limit event indicator is described. A circuit can include receiving a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator. The circuit can further include generating a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles. The latch signal can remain latched at high voltage for a number of clock cycles.

Abstract: Systems and methods for power conversion are described. A power converter can operate under low power mode to supply a first load current from a power management integrated circuit (PMIC). The power converter can transition from low power mode to high power mode by one of activating a tri-state mode of the PMIC prior to activating at least one phase in an external power module and operating PMIC and at least one phase of the external power module simultaneously. The external power module and PMIC can be on separate chips. The power converter can operate under high power mode to supply a second load current from the external power module. The second load current can be greater than the first load current. The power converter can transition from high power mode to low power mode by selectively deactivating phases in the external power module prior to activating the PMIC.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract: A semiconductor device includes a temperature sensor circuit having a sensor element, internal circuits, sensor terminals connected to the sensor element, and normal terminals connected to the internal circuits. A semiconductor inspection apparatus inspects, by using a probe card having first probes and second probes, the semiconductor device mounted on a stage in a first state in which the first probe is in contact with the sensor terminal and the second probe is not in contact with the semiconductor device and in a second state in which the first probe is in contact with the sensor terminal and the second probe is in contact with the normal terminal. The semiconductor inspection apparatus measures an output value of the sensor element in the first state to calculate temperature characteristics of the sensor element, and grasps a temperature of the sensor element in the second state based on the temperature characteristics.

Abstract: A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.