Patents Assigned to RENESAS
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Publication number: 20240356383Abstract: Systems and methods for demodulation in wireless power transfer systems are described. A circuit a device of a wireless power transfer system can sense current from a switching converter, where the sensed current can be associated with an amplitude shift keying (ASK) signal. The circuit can generate a scaled down current of the sensed current. The circuit can generate a voltage signal using the scaled down current, where the voltage signal can be a scaled down voltage of the ASK signal. The circuit can send the voltage signal to a controller of the device. The controller can demodulate the ASK signal using the scaled down voltage.Type: ApplicationFiled: October 24, 2023Publication date: October 24, 2024Applicant: Renesas Electronics America Inc.Inventors: Marco SAUTTO, Fabio di FAZIO
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Patent number: 12125905Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.Type: GrantFiled: June 18, 2020Date of Patent: October 22, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Kaya, Katsumi Eikyu, Akihiro Shimomura, Hiroshi Yanagigawa, Kazuhisa Mori
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Patent number: 12125703Abstract: After a plurality of trenches is formed in an SOI substrate, a side surface of the insulating layer is retreated from a side surface of the semiconductor layer and a side surface of the semiconductor substrate. Next, the side surface of the insulating layer is covered with an organic film and also the side surface of the semiconductor layer is exposed from the organic film by performing an anisotropic etching process to the organic film embedded into an inside of each of the plurality of trenches. Next, each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate is approached to the side surface of the insulating layer by performing an isotropic etching process. Further, after the organic film is removed, an oxidation treatment is performed to each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate.Type: GrantFiled: March 17, 2022Date of Patent: October 22, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Shibun Tsuda
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Patent number: 12126352Abstract: A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.Type: GrantFiled: November 1, 2022Date of Patent: October 22, 2024Assignee: Renesas Electronics CorporationInventors: Wataru Saito, Fukashi Morishita
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Patent number: 12120225Abstract: Example implementations include a method of generating a first authentication code based at least partially on an authentication key and an application key, transmitting to a secure subsystem of the local processing device the authentication key, the application key, and the first authentication code, generating, at the secure subsystem, a second authentication code based at least partially on the authentication key and the application key, and generating, at the secure subsystem, a secure application key, in accordance with a determination that the first authentication code and the second authentication code satisfy an authentication criterion.Type: GrantFiled: September 25, 2020Date of Patent: October 15, 2024Assignee: Renesas Electronics CorporationInventor: Giancarlo Parodi
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Publication number: 20240339848Abstract: Systems and methods for wireless power transfer systems are described. A controller of a device can detect an overvoltage condition associated with direct current (DC) power being outputted by a rectifier. The controller can, in response to detection of the overvoltage condition, the controller can control a phase of a current of alternating current (AC) power being received by the rectifier to cause the current and a voltage of the AC power to be out of phase.Type: ApplicationFiled: April 10, 2023Publication date: October 10, 2024Applicant: Renesas Electronics America Inc.Inventors: Hulong ZENG, Eric Tong Lin HUANG, Chan Young JEONG
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Publication number: 20240339984Abstract: A balun circuit is disclosed. The balun circuit is provided between a transmitter and a common antenna terminal to which the transmitter and a receiver are coupled. The balun includes an inductor L1 coupled at one or both ends to the transmitter, an input node of the receiver, and an inductor L2 provided between ground or a first biasing power supply. The inductor L2 includes an inductor having a mutual inductance with the inductor L1. The inductor L2 is a variable inductor.Type: ApplicationFiled: February 27, 2024Publication date: October 10, 2024Applicant: Renesas Electronics CorporationInventors: Kenichi SHIBATA, Yuichi KUSAKA
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Patent number: 12113105Abstract: A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on upper portion of the base layer; a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter; a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter.Type: GrantFiled: April 14, 2022Date of Patent: October 8, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nao Nagata
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Patent number: 12113041Abstract: In order to reduce on-resistance in a semiconductor device to be used for high current applications, the semiconductor device includes a source terminal lead located between a gate terminal lead and a Kelvin terminal lead in plan view and electrically connected with a source terminal via a plurality of wires.Type: GrantFiled: April 11, 2022Date of Patent: October 8, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Noriko Okunishi, Toshiyuki Hata
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Patent number: 12113428Abstract: A regulator circuit is presented. The regulation circuit (530) has a regulation switch (131), a voltage comparator (537) with predetermined offset voltage and an adjuster. The regulation switch (131) has a first terminal coupled to a current source (132), a second terminal connectable to a load (110), and a control terminal. The voltage comparator (537) compares a sum voltage of the offset voltage added to a voltage at the second terminal with a control voltage at the control terminal, and generates a comparison signal. The adjuster adjusts the voltage at the second terminal based on the comparison signal to control a difference voltage between the control terminal and the second terminal of the regulation switch and to maintain the regulation switch operating in a desired region of operation.Type: GrantFiled: December 6, 2022Date of Patent: October 8, 2024Assignee: Renesas Design (UK) LimitedInventors: Youzhong Liu, Yanzhao Wang, Yanjun Li, Yixuan Ma
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Patent number: 12105506Abstract: A system and method are provided for identification of a combination of sensors suitable for achieving a set of output requirements, enabling assembly thereof. An arrangement of sensors is assembled according to an optimized sensor set, generated to define at least one sensor channel having a threshold value for at least one quality criterion. The sensor sets are generated by down-selection of the sensor channels from a previously tested set of available channels to a subset mapping to a set of required output states. Assignment of a threshold value for each sensor channel is based on a mapping of the value to a target value of a performance metric.Type: GrantFiled: January 25, 2022Date of Patent: October 1, 2024Assignee: Renesas Electronics AmericaInventor: Jeffrey Sieracki
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Patent number: 12105549Abstract: In an embodiment, a voltage reference circuit is disclosed that includes a first transistor circuit that is configured to receive an external supply voltage as an input and to output a first voltage and a chopper circuit that is configured to receive a second voltage as an input and to output a voltage reference. The chopper circuit has a breakage threshold. The voltage reference circuit further includes a second transistor circuit that is configured to receive the first voltage as an input and to output the second voltage at a value that is less than or equal to the breakage threshold of the chopper circuit.Type: GrantFiled: March 30, 2022Date of Patent: October 1, 2024Assignee: RENESAS ELECTRONICS AMERICA INC.Inventor: Sunil Satish Rao
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Patent number: 12107138Abstract: To improve a reliability of a nonvolatile memory cell including a ferroelectric film. The nonvolatile memory cell MC includes a paraelectric film IL formed on a semiconductor substrate SUB, the ferroelectric film FE formed on the paraelectric film IL, a gate electrode GE formed on the ferroelectric film FE, a high dielectric constant film HK formed on the ferroelectric film FE such that the high dielectric constant film HK cover side surfaces of the gate electrode GE, and a source region SR and a drain region DR formed in an upper surface of the semiconductor substrate SUB such that the ferroelectric film FE is sandwiched between the source region SR and the drain region DR. A relative dielectric constant of the high dielectric constant film HK is higher than a relative dielectric constant of the ferroelectric film FE.Type: GrantFiled: November 29, 2022Date of Patent: October 1, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshiyuki Kawashima
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Publication number: 20240321824Abstract: Circuits and devices for a motor driver are described. A hybrid integrated circuit (IC) can include a driver IC, a first IC, and a plurality of second ICs. The first IC can include a plurality of high-side metal-oxide-semiconductor field-effect transistors (MOSFETs). The first IC can further include a common drain terminal connected to drains of the plurality of high-side MOSFETs. Each one of the plurality of second ICs can include a respective low-side MOSFET. The hybrid IC can further include a first set of bonding wires connecting the driver IC to the first IC. The hybrid IC can further include a second set of bonding wires connecting the driver IC to the plurality of second ICs. The hybrid IC can further include a third set of bonding wires connecting the first IC to the plurality of second ICs.Type: ApplicationFiled: March 21, 2023Publication date: September 26, 2024Applicant: Renesas Electronics America Inc.Inventors: Tetsuo SATO, Jianghong DING, Yonggoo EOM
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Publication number: 20240322590Abstract: A method may include receiving power from a power adapter having a power adapter current limit, providing power from the power adapter to a load having a load current at a first load current level that is less than or equal to the power adapter current limit; generating a first periodic current through an inductor in a forward direction; detecting the load having the load current at a second load current level that may be greater than the adapter power current limit; decreasing the forward current level of the first periodic current; and generating a second periodic current through the inductor in a reverse direction to provide power from the battery module to the load. The second periodic current may be initiated in the reverse direction when the first periodic current in the forward direction reaches the zero current level.Type: ApplicationFiled: March 23, 2023Publication date: September 26, 2024Applicant: Renesas Electronics America Inc.Inventors: Shahriar Jalal NIBIR, Sungkeun LIM, Yen-Mo Chen, Chong HAN, Heonyoung KIM
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Patent number: 12099920Abstract: A first voltage application circuit applies a first voltage determined to have a first voltage value to a first wiring connected to an asymmetrical memory cell. A second voltage application circuit applies a second voltage determined to have a second voltage value to a second wiring connected to the asymmetrical memory cell. When receiving a first input value from a first terminal, a voltage control circuit fixes the second voltage value and changes the first voltage value with a positive inclination with respect to the first input value within a range equal to or higher than the second voltage value. When receiving a second input value from a second terminal, the voltage control circuit fixes the first voltage value and changes the second voltage value with a negative inclination with respect to the second input value within a range equal to or lower than the first voltage value.Type: GrantFiled: April 9, 2021Date of Patent: September 24, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Junichi Suzuki
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Device and method of secure decryption by virtualization and translation of physical encryption keys
Patent number: 12099452Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.Type: GrantFiled: June 16, 2023Date of Patent: September 24, 2024Assignee: Renesas Electronic CorporationInventors: Ahmad Nasser, Eric Winder -
Patent number: 12100972Abstract: Systems, apparatuses, and methods for detecting a foreign object on a wireless power charging region are described. A circuit can detect an object inductively coupled to a wireless power transmitter. The circuit can further measure an input parameter prior to a power transfer stage, the input parameter can be one of an input current and an input power. The circuit can further compare the measured input parameter with a predetermined value. The circuit can further determine whether the object is a foreign object or the wireless power receiver based on a result of the comparison between the measured input parameter with the predetermined value.Type: GrantFiled: August 9, 2022Date of Patent: September 24, 2024Assignee: Renesas Electronics America Inc.Inventors: Chan Young Jeong, Tao Qi, Young Chul Ryu, Kwangmuk Choi, Pooja Agrawal, Krishal Jaswantsinh Solanki, Adnan Dzebic
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Publication number: 20240310863Abstract: A capless regulator circuit is provided. The regulator circuit includes a power transistor that controls the supply of current to an external output terminal connected to a load; a monitor transistor provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied, and through which a current corresponding to the voltage of the external output terminal flows; a first constant current source that is provided in series with the monitor transistor and generates a first voltage according to the difference between the first current and a first constant current; and a cascode circuit that generates a second voltage that amplifies the first voltage and supplies it to the gate of the power transistor.Type: ApplicationFiled: February 27, 2024Publication date: September 19, 2024Applicant: Renesas Electronics CorporationInventors: Atsushi TSUDA, Kosuke YAYAMA
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Publication number: 20240313270Abstract: A battery device is disclosed. The battery device includes a lithium-ion battery cell; a strain gauge attached to a surface of the battery cell; a temperature sensor detecting a temperature of the battery cell; and a measurement device calculating an SOC (State of Charge) of the battery cell a strain amount based on the temperature detected by the temperature sensor and a strain amount of the strain gauge changed according to a volume change due to charge and discharge of the battery cell.Type: ApplicationFiled: March 15, 2024Publication date: September 19, 2024Applicant: Renesas Electronics CorporationInventors: Masaki HOGARI, Hirofumi MAEDA, Hiroshi TADOKORO, Kenji NOGUCHI, Hiroyasu KOIKE
