Abstract: A system of a transmitter device for the transmission of an analog signal and/or digital data provided to the system at a transmitter interface of the transmitter device is disclosed. The transmitter interface includes at least two parallel information lines. The system includes a receiver device with a receiver interface to receive the analog signal and/or digital data. The receiver interface includes the same number of parallel information lines. A transmitter protocol unit processes the analog signal and/or digital data to generate a serial data stream that includes reconstruction information. Transmission is performed via an electromagnetic field. The receiver device includes a receiver protocol unit to process and reconstruct the received serial data stream. The transmitter device is powered by electrical power provided at two power lines of the transmitter interface. The receiver device is adapted to provide power received from the transmitter device using a power recovery unit.

Abstract: A system including a power device and a portable device for wireless charging of a battery of the portable device, which power device includes a first transmitter stage and a second transmitter stage. The first transmitter stage includes an antenna configured to receive power adjustment information from a first receiver stage of the portable device to increase or to decrease the power transmitted by a first magnetic field emitted with the antenna of the first transmitter stage. The first receiver stage includes an antenna exposed to the first magnetic field and connected via a matching stage to a rectifier stage to rectify an antenna signal and to provide an input voltage at an input pin of a charge stage that provides a first charge current at a first output pin connected to the battery to charge the battery in charging cycles.

Abstract: A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

Abstract: A reliability prediction method includes: calculating a change of each of a plurality of alloy phases at a bonding portion between an electrode pad and a bonding wire; setting a generation of a metal oxide phase caused by a corrosion reaction, based on an initial crack structure of the bonding portion; calculating an elastic strain energy at each of specified portions of the bonding portion; setting a progress of a crack, based on the elastic strain energy at each of the specified portions; and predicting a lifetime of the semiconductor device, based on a length of the crack due to the progress of the crack.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: In an embodiment, an apparatus is disclosed. The apparatus includes a battery and a wireless power receiver. The wireless power receiver includes a controller and a memory subsystem. The controller is configured to perform a handshake with a wireless power transmitter. The handshake corresponds to a temporary suspension of a power transfer between the wireless power transmitter and the wireless power receiver. The controller is configured to transition the wireless power receiver from a power transfer mode, in which power is transferred wirelessly from the wireless transmitter to the wireless receiver, to a cloak mode, in which the power transfer is suspended, based on the handshake and obtain a supply of power from the battery based on the transition to the cloak mode, the power being configured for use by the controller to maintain power transfer state information about the temporarily suspended power transfer in the memory subsystem.

Abstract: Apparatuses, devices, and methods for operating a multi-level voltage converter are described. A circuit can, in response to a completion of a state of the multi-level voltage converter, output an indication that indicates whether a voltage of a flying capacitor in a multi-level voltage converter reaches a reference voltage or fails to reach the reference voltage. The completed state can be one of a charge state and a discharge state. A controller can, in response to the indication indicating the voltage of the flying capacitor fails to reach the reference voltage, repeat the completed state to operate the multi-level voltage converter.

Abstract: A method, apparatus and non-transitory computer-readable medium of regulating current within a battery charging circuit. The apparatus including a first current sense resistor configured to sense a first current value at a first port, a second current sensor resistor configured to sense a battery discharge current value output from a battery, and a processor configured to, in response to a short circuit or malfunction at the first current sense resistor, use the battery discharge current value to determine an output current limit and to limit the current at the first port according to the output current limit.

Abstract: A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member.

Abstract: Systems, devices, and methods for isolating digital signals are described. A carrier signal can be modulated using a first signal to generate a first modulated signal. The carrier signal and the first modulated signal can be transmitted through a forward path in an isolation barrier, where transmitting the carrier signal through the isolation barrier can transform the carrier signal into a delayed carrier signal. The first modulated signal can be demodulated to recover the first signal. The delayed carrier signal can be modulated using a second signal to generate a second modulated signal. The delayed carrier signal and the second modulated signal can be transmitted through a return path in the isolation barrier, where the return path and the forward path has opposite directions.

Abstract: A switching converter is presented. The switching converter has a high side power switch coupled to a low side power switch at a switching node, a driver and a timing circuit. The driver generates a drive signal having a on-time to drive the high side power switch. The timing circuit generates a control signal to adjust the on-time during a load transient period.

Abstract: A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.

Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

Abstract: A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among “n×m” weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

Abstract: A first insulating film is formed on a semiconductor substrate in each of a first region in which a memory transistor is to be formed, a second region in which a selection transistor is to be formed, a third region in which a high-withstand-voltage transistor is to be formed, and a fourth region in which a low-withstand-voltage transistor is to be formed. Subsequently, the first insulating film in each of the first and second regions is removed. A second insulating film is formed on the semiconductor substrate in each of the first and second regions. A third insulating film having a trap level is formed on the second insulating film. The third insulating film in the second region and the second insulating film in the second region are removed. A fourth insulating film is formed on the third insulating film and on the semiconductor substrate in the second region.

Abstract: Battery charger systems and apparatuses are described. In an example, an apparatus may include a first controller, a first port connected to the first controller, a first charger module connected to the first controller, a second controller, a second port connected to the second controller, and a second charger module connected to the second controller. The first controller may be configured to form a first connection path between the first charger module and the second port via the second controller. The first controller may be further configured to form a second connection path between the second charger module and the first port via the first controller.

Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.

Abstract: An asynchronous finite state machine circuit comprising state circuitry configured to be in one of a plurality of states, and transition between states, wherein the asynchronous finite state machine is configured to detect that a current state is stable before the state circuitry can transition to a next state.

Abstract: Systems and methods for injecting a current into are described. A switch converter can include a high-side switch and a low-side switch. A driver circuit can be configured to drive the high-side switch and the low-side switch in the switch converter. A controller can be configured to provide control signals to control the driver circuit. The driver circuit can further include a circuit configured to inject a current dip into a gate current outputted by the driver circuit to drive at least one of the high-side switch and the low-side switch.