Abstract: A power converter which has a reservoir capacitor, a first flying capacitor, and first and second inductors coupled to a network of switches is presented. A driver is adapted to drive the network of switches with a sequence of states during a drive period. The power converter is operable in a first mode to deliver an output current using both the first and second inductors and a second mode to deliver the output current using the first inductor and without using the second inductor. When a load current is above a threshold value, the driver drives the network of switches in a first sequence of states to operate the power converter in the first mode. When the load current is equal or below the threshold value, the driver drives the network of switches in a second sequence of states to operate the power converter in the second mode.

Abstract: Methods and systems for operating a voltage regulator are described. A integrated circuit can be configured to adjust at least one of a deadtime parameter and a drive strength parameter of a power stage based on at least one of an input voltage being provided to a power stage, a switch node voltage of the power stage, and an output current of the power stage. A controller of the power stage can be further configured to adjust a deadtime of the power stage based on adjustment of the deadtime parameter. The controller can be further configured to adjust a drive strength of the first driver and the second driver based on adjustment of the drive strength parameter.

Abstract: Exemplary embodiments may include a device with an input power component, a system supply component, an inductive charger component operatively coupled to the input component and the system component, and a direct charger component operatively coupled to the inductive charger and the system component. Exemplary embodiments may further include an input node of the inductive charger component and an input node of the direct charger component operatively coupled to an output node of the input power component at a first device node. Exemplary embodiments may also include a method of receiving an input power signal, obtaining a charging condition, entering a first charging state, in accordance with the obtained charging condition satisfying a first charging condition, and entering a second charging state, in accordance with the obtained charging condition satisfying a second charging condition.

Abstract: Semiconductor device includes a well region formed in an active region of a semiconductor substrate, a gate electrode formed on the well region via a gate dielectric film, and a source region and a drain region formed in the well region. At the vicinity of both end portions of the active region in the first direction, a first region and a second region having the same conductivity type as the well region and having impurity concentration higher than that of the well region are formed in the well region. The first region and the second region are spaced from each other in a second direction perpendicular to the first direction, and at least a portion of each of them is located under the gate electrode. The first region and the second region are not formed at the center portion of the active region in the first direction.

Abstract: A power converter including an inductor, a first power switch, a second power switch, a third power switch, a fourth power switch, a sixth power switch, a first flying capacitor, a third flying capacitor, a seventh power switch, an eighth power switch, a ninth power switch, a tenth power switch, a twelfth power switch, a second flying capacitor, and a fourth flying capacitor.

Abstract: Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.

Abstract: A display control device and a display control method capable of displaying a desired image regardless of a state of wireless communication are provided. A wireless control unit causes an external apparatus to draw a first image in accordance with input information. A first unit acquires the first image via the wireless communication and displays the first image on a display apparatus. A second unit causes a GPU to draw a second image in accordance with the unput information and displays the second image on the display apparatus. A switching unit determines whether a received radio wave is in a good state or a bad state, select the first unit when a determination result is that the received radio wave is in the good state, and select the second unit when the determination result is that the received radio wave is in the bad state.

Abstract: A semiconductor device includes a galvanic isolator; a transmitting circuit that transmits a transmission signal via the galvanic isolator; a receiving circuit that receives a received signal corresponding to the transmission signal via the galvanic isolator; an encoding circuit that encodes two input signals and generates the transmission signal; and a decoding circuit that decodes the two input signals from the received signals.

Abstract: A wireless transmitter coordinates changes in the transmitter's input or output voltages with changes in the transmitter's operating frequency to counteract the transmitter's output power changes while changing the voltages. When the voltages are being increased, the output frequency is moved away from the resonant frequency. Consequently, the output power increase due to the increased voltages is restrained by the frequency change. Before or after the voltage increase, increased output power can be obtained by changing the output frequency while the input and output voltages are held constant or near constant. Some embodiments follow similar procedures when reducing the transmitter's input or output voltages. Calibration is performed before power transfer to determine suitable voltage and frequency profiles for voltage change operations. Other features are also provided.

Abstract: A control circuit receives a command from outside and causes an arithmetic unit to perform arithmetic operation M times (M is an integer of 2 or more) by using input data from outside and calculated data held in a memory, thereby making the arithmetic unit and the memory function as an IIR filter. The IIR filter is a filter capable of determining output data by arithmetic operation of K times out of the M times (K<M). The control circuit receives the command from outside and then causes the arithmetic unit to perform the arithmetic operation K times in advance, thereby determining the output data and outputting the output data to outside at that time.

Abstract: The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

Abstract: Methods and systems for operating a transceiver are described. A transceiver can include an upconverting mixer, a downconverting mixer, a controller, and an envelope detector. The upconverting mixer can mix an input signal with a local oscillator (LO) signal to generate a transmitter signal. The envelope detector can receive the transmitter signal outputted from the upconverting mixer and output an envelope of the transmitter signal to an output line of the downconverting mixer. The envelope can indicate at least one of a leaked LO signal and an image signal. The controller can receive a calibration parameter that is based on at least one of the leaked LO signal and image signal and calibrate the upconverting mixer based on the calibration parameter.

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: The magnetic pole position of the rotor is estimated with high accuracy at the initial start of a three-phase motor of the sensorless system. Semiconductor device for driving and controlling the three-phase motor of the sensorless system have a detector connected to the three-phase output nodes of the inverter circuit and the virtual neutral point (or neutral point), and detecting a voltage generated in the output node of the non-energized phase of the three-phase. Controller applies the initial drive voltage by the inverter circuit to any two phases of the three-phase motor based on the estimated position of the magnetic pole of the rotor in the stop state. Controller estimates the position of the rotor based on a difference voltage detected by the detector in a driving voltage applying period and a regeneration period immediately after or immediately before the driving voltage applying period.

Abstract: Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.

Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.

Abstract: A method of automated feedforward filter design comprising designing a feedforward filter for a system implementing active noise cancelling is described. The method includes designing the feedforward filter by determining a filter transfer function of the feedforward filter. The filter transfer function is determined using a least square method. The method also includes determining the filter transfer function by defining a target transfer function of the feedforward filter and applying the least square method using the target transfer function to determine a filter expression for the filter transfer function. The least square method is a weighted least square method.

Abstract: In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.

Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.

Abstract: Systems and methods for wireless power transfer systems are described. A controller of a device can communicate with a power device by a first modulation mode. The controller can detect a failure condition between the controller and the power device. The controller can, in response to the detection of the failure condition, communicate with the power device by a second modulation mode. The first modulation mode can include capacitive modulation and the second modulation mode can include resistive modulation.