Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

Abstract: A semiconductor device includes a main circuit and a peripheral circuit inputting/outputting a signal from/to the main circuit, the main circuit including: a memory cell array; a sense amplifier; a first output holding circuit holding the read data output from the sense amplifier; a second output holding circuit receiving the read data as its input output from the first output holding circuit; and a delay circuit outputting a delay signal for activating the second output holding circuit to be later than the first output holding circuit. The delay circuit includes an element applying a load capacitance to a wiring of the delay signal. A power-supply voltage being a first voltage is supplied to the memory cell array, the sense amplifier and the first output holding circuit. A power-supply voltage being a second voltage is supplied to the delay circuit, the second output holding circuit and the peripheral circuit.

Abstract: An apparatus includes a plurality of transceiver circuits, each comprising one or more phase shifter circuits. The phase shifter circuits may be configured to make a phase change by switching at least one of a capacitance value and an inductance value in response to a control signal. A characteristic impedance and the phase of each phase shifter circuit are correlated such that after the phase change, a value of the characteristic impedance is maintained at a predefined value.

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.

Abstract: A semiconductor device includes a first transistor that flows a load current to an external load; a current generation circuit that outputs a current corresponding to a power consumption generated in an overheat detection target when the load current flows the overheat detection target; a resistor-capacitor-network comprising a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance of the overheat detection target, and having one end coupled to the current generation circuit; an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor-network; and a voltage source that sets a voltage of the connection point of the current generation circuit and the resistor-capacitor-network to a predetermined voltage.

Abstract: In an embodiment, an apparatus is disclosed that includes a first battery management circuit. The first battery management circuit is configured to measure a voltage of a first battery cell of a battery pack and to generate a first voltage measurement based at least in part on the measured voltage of the first battery cell. The first battery management circuit is configured to receive a bit of a first response from a second battery management circuit. The bit of the first response is generated by the second battery management circuit based at least in part on a measured voltage of a second battery cell of the battery pack. The first battery management circuit is configured to sum the bit of the first response with a corresponding bit of the first voltage measurement and to provide the summed bit to a third battery management circuit as part of a second response.

Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

Abstract: A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

Abstract: The semiconductor device includes a control unit having redundant processors, a memory storing target data, a secure memory storing a key used for encryption or decryption processing, an cryptographic unit, a secure processor instructing cryptographic processing to the cryptographic unit in response to a request from the control unit, a first bus coupled to the control unit, the memory, the cryptographic unit, and the secure processor, and a second bus coupled to the secure memory, the cryptographic unit, and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, the cryptographic unit includes a plurality of cryptographic processors that independently perform cryptographic processing on target data using a key based on an instruction, and each of the plurality of cryptographic processors includes a data transfer unit that performs data transfer with the memory via the error detection mechanism.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.

Abstract: Systems and methods for calibrating a wireless power transmitter is described. A wireless power transmitter can include a controller and an amplifier module. The amplifier module can include an amplifier configured to amplify a voltage converted from a current proportional to power consumed by a wireless power transmitter, and a circuit connected to the amplifier. The circuit can be configured to receive a control signal from the controller. The circuit can be further configured to perform time division multiplexing on an output of the amplifier according to the control signal. A time division multiplexed output of the amplifier can include calibration data of the amplifier. The amplifier can be configured to output the time division multiplexed output to the controller.

Abstract: A network device comprising a set of queues and a time-aware shaper which comprises a set of transmission gates and gate control instructions. The gate control list comprises a set of individual gate control lists, each individual gate control list configured to control a respective gate and which comprises a sequence of entries, each entry comprising a duration of time.

Abstract: The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

Abstract: A semiconductor device includes: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; an optical waveguide formed on the insulating layer, extending in a first direction in a plan view, and being made of silicon; and an interlayer insulating film formed on the insulating layer to cover the optical waveguide. In this case, a crystal surface of a side surface of the optical waveguide is a (111) surface.

Abstract: A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Abstract: A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.