Patents Assigned to RENESAS
  • Data processing apparatus and memory protection method
    Patent number: 11868277
    Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Sugita
  • Method and system for full cycle error correction of inductor current measurement for switching regulators
    Patent number: 11867788
    Abstract: Example implementations include a method of generating a ramp down compensation voltage based at least partially on the a current sense voltage and an inductor voltage of an inductor at an inductor node, applying the ramp down compensation voltage to the inductor node, and in accordance with a first determination that the valley current sense voltage and the inductor voltage are not equal, modifying a predetermined capacitance of a system capacitor operatively coupled to the inductor node to a first modified capacitance.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 9, 2024
    Assignee: Renesas Electronics America Inc.
    Inventor: Michael Ding
  • Semiconductor device
    Patent number: 11868654
    Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takanori Moriyasu, Kazuo Yoshihara, Takayuki Nishiyama
  • Register clock driver with chip select loopback
    Patent number: 11868172
    Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Zhihan Zhang, Yuan Zhang
  • Method of manufacturing semiconductor device
    Patent number: 11860225
    Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukumi Unokuchi, Toshitsugu Ishii
  • IN-SITU SILENT FAULT DETECTION FOR BUZZERS
    Publication number: 20230419818
    Abstract: In an embodiment, a semiconductor device is disclosed. The semiconductor device includes a plurality of output pins. Each of the output pins is electrically connected to an input pin of a buzzer and to a buzzer driver. The buzzer driver is configured to cause the buzzer to emit an audible sound. The semiconductor device further includes a plurality of ground switches. Each ground switch is configured to connect a corresponding output pin of the plurality of output pins to ground when closed. The semiconductor device further includes a current generator that is configured to supply a test current to a given output pin of the plurality of output pins and a clamp switch that is configured to connect the given output pin to an analog-to-digital converter.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 28, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Lokesh KUMATH, Muthukumaran CHANDRASEKARAN, Harley Franklin BURGER, JR.
  • One-line synchronous interface
    Patent number: 11855800
    Abstract: Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: December 26, 2023
    Assignee: Renesas Electronics America Inc.
    Inventors: Leonid Goldin, Greg Anton Armstrong
  • SEMICONDUCTOR DEVICE
    Publication number: 20230412169
    Abstract: A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 21, 2023
    Applicant: Renesas Electronics Corporation
    Inventor: Koji TAKAYANAGI
  • INDUCTIVE POSITION SENSOR FOR DETECTING A LINEAR OR ANGULAR MOVEMENT OF A CONDUCTIVE TARGET
    Publication number: 20230408297
    Abstract: An inductive position sensor for detecting a linear or angular movement of a conductive target, including: a transmitter coil; a first receiver coil and a second receiver coil, wherein the first receiver coil and the second receiver coil have a linear or angular shape and define the detection range of the inductive linear or arc position sensor; a first conductive target and a second conductive target; the first conductive target and the second conductive target each have a linear or angular shape extension of half the detection range of the inductive position sensor and are spaced from each other by half the detection range of the inductive position sensor.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 21, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Gentjan QAMA, Andreas Leo BUCHINGER, Bence GOMBOR, Rudolf PICHLER, Harald HARTL
  • Semiconductor device and method for protecting bus
    Patent number: 11847078
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: December 19, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki
  • Semiconductor device, electronic control unit, verification method of electronic control unit and manufacturing method of electronic control unit
    Patent number: 11845387
    Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: December 19, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayuki Daito
  • Ripple reduction circuit for use with a power supply
    Patent number: 11848601
    Abstract: A ripple reduction circuit for use with an AC/DC power supply providing an output voltage to a load is presented. The ripple reduction circuit includes an input terminal for receiving the output voltage and a low pass filter. The low pass filter is used to filter an AC component of the output voltage to obtain a filtered DC voltage. The ripple reduction circuit generates a reference current based on the filtered DC voltage and a control voltage having an AC component in phase with the AC component of the output voltage.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 19, 2023
    Assignee: Renesas Design (UK) Limited
    Inventor: Yu-Chin Lin
  • Semiconductor device
    Patent number: 11843371
    Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 12, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Fumiaki Yanagihashi
  • Digital Demodulation for Wireless Power
    Publication number: 20230396472
    Abstract: In an embodiment, a semiconductor device is disclosed that includes at least one processing device and firmware including a dynamic demodulation engine. The dynamic demodulation engine, when executed by the at least one processing device, is configured to obtain a digital signal waveform, dynamically select a bit detection method based at least in part on a characteristic of the digital signal waveform, perform demodulation of the digital signal waveform using the selected bit detection method and generate decoded packets based at least in part on the demodulation.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Damla Solmaz Acar, Pooja Agrawal, Jure Menart, Tao Qi, Mihail Jefremow, Gustavo James Mehas
  • WRITE PROTECT FUNCTION WITH SECURE CERTIFICATE AUTHENTICATION
    Publication number: 20230394160
    Abstract: In an embodiment, an apparatus is disclosed that includes a memory slot including a certificate chain corresponding to an entity and a memory block. The memory block has protection enabled. The apparatus includes a processing device. The processing device is configured to receive a request message to clear protection for the memory block from a computing device of the entity. The request message includes a signature generated based at least in part on a private key of the entity. The processing device is configured to determine a public key corresponding to the entity based at least in part on the certificate chain, determine that the signature is valid based at least in part on the public key, determine that the protection for the memory block corresponds to the certificate chain and clear the protection for the memory block.
    Type: Application
    Filed: December 15, 2022
    Publication date: December 7, 2023
    Applicant: Renesas Electronics America Inc.
    Inventor: Shwetal Arvind Patel
  • Message handler
    Patent number: 11838393
    Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Dnyaneshwar Kulkarni, Thorsten Hoffleit
  • QUADRATURE COMMUNICATION FOR WIRELESS POWER TRANSFER
    Publication number: 20230388174
    Abstract: Systems and methods for demodulating a signal is described. A device can receive a modulated signal that encodes data. The device can sample a voltage of the modulated signal to generate a plurality of samples in digital domain. The device can determine in-phase data and quadrature data of the plurality of samples. The device can determine amplitude data and phase data based on the in-phase data and the quadrature data. The device can decode the amplitude data and phase data into digital symbols that represent the data encoded in the modulated signal.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 30, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Damla Solmaz ACAR, Mihail JEFREMOW, Jure MENART, Pooja AGRAWAL, Amit BAVISI, Gustavo James MEHAS
  • SEMICONDUCTOR DEVICE
    Publication number: 20230387924
    Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 30, 2023
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke IMANAKA, Atsushi MOTOZAWA
  • Semiconductor device and error detection methods
    Patent number: 11831337
    Abstract: A semiconductor device includes a syndrome generation circuit configured to generate a syndrome code based on data and an error correction code corresponding to the data, an error determination circuit configured to detect a 1-bit error in the data based on the syndrome code, and multi-bit error detection circuit configured to determine whether the data detected to have 1-bit error includes a multi-bit error by using an error address of the data detected to have 1-bit error and an error syndrome code of the data detected to have 1-bit error.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: November 28, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Ishibashi, Hiroyuki Hashimoto
  • Semiconductor device and method of manufacturing the same
    Patent number: 11830944
    Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 28, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Koshimizu, Yasutaka Nakashiba