Abstract: A wiring substrate includes a side-wall electroconduction layer and a land. The side-wall electroconduction layer is formed on the side-wall of a through hole formed in the substrate. The land is an electroconduction layer connected with the side-wall electroconduction layer in which only the land portion as a minimum necessary portion used for wiring is formed to the surface of the substrate. Unnecessary portion of the land other than the land portion is eliminated.

Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.

Abstract: A method of manufacturing a semiconductor device at a good manufacturing efficiency and at a low cost while suppressing the occurrence of voids in the sealing region, the method including the steps of (A) bonding external connection terminals of a semiconductor chip to wirings of a film substrate by hot press bonding, and (B) resin sealing the periphery of the bonded portion of the semiconductor chip and the film substrate, in which the bonding step (A) is performed in a state of adsorbing a portion of the film substrate facing the semiconductor chip from the side opposite the bonding side of the semiconductor chip, and the resin sealing step (B) is performed in a state where the temperature of the semiconductor chip and the film substrate is lowered press is no thermal expansion of the film substrate.

Abstract: A method of manufacturing a semiconductor device comprises: determining whether or not the viscosity of a sealing resin at a first temperature lower than the melting temperature of the sealing resin is less than or equal to a first reference value which prevents poor sealing from occurring at the first temperature, for each lot in which the corresponding sealing resin is manufactured; selecting the sealing resin of the lot when the viscosity of the sealing resin at the first temperature is less than or equal to the first reference value; introducing the sealing resin selected in selecting the sealing resin into a mold of a compression molding apparatus; and sealing a semiconductor chip mounted over a substrate with the sealing resin by compression molding using the mold heated at a second temperature higher than the first temperature after introducing the sealing resin.

Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.

Abstract: A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.

Abstract: A semiconductor device manufacturing equipment includes a plurality of heat treatment plates for performing a post-exposure bake (PEB), a first storage section for storing a first relation, said first relation being an association relation between post-development resist pattern dimensions and a preset temperature during the PEB, a second storage section for storing a second relation, the second relation being an association relation between post-etching pattern dimensions and the preset temperature during the PEB, a primary correction section for obtaining post-development resist pattern dimension data for each of a plurality of first substrates processed separately by the plurality of heat treatment plates, and for primarily correcting the preset temperature for each of the plurality of heat treatment plates based on the first relation; and a secondary correction section for obtaining post-etching pattern dimension data for each of a plurality of second substrates.

Abstract: A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data.

Abstract: A source driver is supplied with a mode switch signal specifying an applied inversion driving method from among horizontal one-dot inversion driving, first horizontal n-dot inversion driving in which a number of outputs does not disturb regularity of a polarity pattern of data signals, and second horizontal n-dot inversion driving in which a number of outputs disturbs regularity of a polarity pattern of data signals. The source driver supplies data signals to data lines. The polarity pattern of the data signals depends on a polarity signal and the applied inversion driving method specified by the mode switch signal. The source driver supplies the polarity signal to a next source driver in the case of the horizontal one-dot inversion driving or the first horizontal n-dot inversion driving, and supplies the polarity signal whose polarity is inverted to the next source driver in the case of the second horizontal n-dot inversion driving.

Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.

Abstract: A microcomputer according to the present invention includes: a CPU (Central Processing Unit) that has a plurality of modes including a usual operational mode and a STANDBY mode, a clock supply being stopped in the STANDBY mode; a clock generation circuit that generates a clock supplied to the CPU; and a control circuit that monitors a mode of the CPU, determines a mode to which the CPU should transit according to the mode of the CPU and a type of an interruption request to the CPU, and controls the clock generation circuit according to the determined mode.

Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device.

Abstract: A circuit operation verification system has: a computer; a programmable logic device in which a device under test is configured; and a test bench section configured to perform operation verification of the device under test. The test bench section has: a software section that is implemented by the computer executing software; and a hardware section configured in the programmable logic device together with the device under test. The hardware section has a hardware function that generates a test pattern and inputs the test pattern to the device under test to perform the operation verification. The hardware function is controllable by changing a control parameter, and the software section variably sets the control parameter.

Abstract: A semiconductor device and manufacturing method to effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.

Abstract: A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR1) in the substrate adjacent the first side gate; a second impurity implantation region (IIR2) formed in the substrate on a side of the second side gate; and a channel region between IIR1 and IIR2. The channel region includes a first region corresponding to a boundary between the CAL and the substrate; a select side region between the first region and IIR1; and an assist side region between the first region and IIR2. The select side region is longer than the assist side region.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: A wireless communication apparatus receives a signal with a no signal section inserted between OFDM symbols and includes an overlap addition number table unit and an overlap addition unit. The overlap addition number table unit associates band information specifying a frequency band to transmit a signal and an overlap addition number specifying a number of samples in the no-signal section to be overlap-added to an OFDM symbol. The overlap addition unit adds data to a beginning of the OFDM symbol using the overlap addition number table, the data corresponding to the overlap addition number determined according to the band information.

Abstract: An electronic component contactor includes a plurality of contact pins, a housing that encases and determines positions of the plurality of contact pins, and a buffer member that buffers against the behavior of the contact pins. The contact pins each includes a base portion, a stretch portion that stretches from the base portion in an arc shape, a contact portion that is formed in the stretch portion, and a load receiving portion. The housing includes a support base in which a surface supporting the buffer member is formed to be flat. The buffer member is formed in a sheet-like shape. A portion of the buffer member that faces the load receiving portion is supported by the support base.

Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.