Abstract: A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer.

Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.

Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.

Abstract: A cryptography processing device has: a round processing unit configured to obtain a processing-object data and generate an intermediate data by applying round processing to the processing-object data; a random number generation unit configured to generate a random number data; a memory circuit in which the intermediate data or the random number data is stored; and a selection control unit configured to select which one of the intermediate data and the random number data is to be stored in the memory circuit. The selection control unit selects the data to be stored in the memory circuit such that the random number data is stored after the intermediate data is stored.

Abstract: Provided is a physical layer circuit. Upon detecting a connection recognition signal from an output of a differential input terminal, a first detection circuit outputs a first control signal for allowing an upper layer to output a power supply control signal for turning on a power supply of each of a receiver circuit and a recovery conversion circuit. Upon detecting “input absent” based on the bit configuration of parallel data, a second detection circuit outputs a second control signal for allowing the upper layer to output the power supply control signal for turning off the power supply of each of the receiver circuit and the recovery conversion circuit. A control circuit turns off a power supply of the first detection circuit when the second detection circuit detects “input present”, and turns on the power supply of the first detection circuit when the second detection circuit detects “input absent”.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: A solid-state imaging device includes: a photoelectric converting section comprising a photo-diode; a charge storage section; a charge transfer section; a first control gate section provided between the photoelectric converting section and the charge storage section to control transfer of a signal charge from the photoelectric converting section to the charge storage section; and a second control gate section provided between the charge storage section and the charge transfer section to control transfer of the signal charge from the charge storage section to the charge transfer section. The charge storage section includes: a first region formed on a side near to the first control gate section; and a second region formed on a side near to the second control gate section and configured to have a channel potential increased more than that of the first region. The second region is configured to hold the signal charge in a pinning condition.

Abstract: A semiconductor device includes at least one semiconductor element having a semiconductor stack containing a channel layer and a cap layer and a lower electrode and an upper electrode formed over a semiconductor stack, and at least one protective element having the semiconductor stack in common with the semiconductor element for protecting the semiconductor element. The protective element includes a recessed portion that penetrates the cap layer in the direction of the thickness, an insulation region formed in the semiconductor stack from the bottom of the recessed portion 221 in the direction of the thickness, and a pair of ohmic electrodes and formed on both sides of the recessed portion and connected to the cap layer.

Abstract: A regulator including a differential amplifier including a differential input stage that differentially receives a reference voltage and an output terminal voltage of the regulator, a drive transistor that has an output connected to an output terminal of the regulator and that has a control terminal connected to an output of the differential amplifier, a first transistor connected between the control terminal of the drive transistor and a first power supply terminal and a second transistor connected between the control terminal of the drive transistor and a second power supply terminal, wherein a control terminal of the first transistor and a control terminal of the second transistor are connected to a first control signal and a second control signal, respectively, the first transistor being on-off controlled by the first control signal and the second transistor being on-off controlled by the second control signal.

Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.

Abstract: It is possible to achieve the above interface structure stabilization by forming a structure in which a fraction of Ni atoms are substituted with Pt atoms only in the first interface layer, thereby lowering the interface energy while suppressing the variation of the characteristics of NiSi and NiSi/Si interface to the minimum extent. Therefore, it is possible to contribute to the improvement of the yield ratio of elements or the improvement of reliability through the stabilization of the crystal phase of NiSi. The NiSi is formed, for example, on the surface layer of a source drain in a transistor.

Abstract: An exemplary aspect of the present invention is a current limiting circuit including: an output transistor that controls a current flowing to a load from a power supply; a current sense transistor through which a current dependent on a current flowing through the output transistor flows; a sense resistor connected in series with the current sense transistor; a potential difference detection unit that detects a potential difference generated between both ends of the sense resistor; a constant current generation unit that supplies a constant current to the potential difference detection unit; and a control unit that controls a conduction state of the output transistor based on a control voltage generated based on the potential difference and the constant current, in which the sense resistor is disposed so as to surround the potential difference detection unit.

Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.

Abstract: A nonvolatile semiconductor storage device includes: a word line; a reading circuit; and a failure detection circuit. The word line is connected to gates of a plurality of nonvolatile memory cell transistors. The reading circuit is connected to one end of the word line and supplies one of a reading selection voltage and a reading non-selection voltage to the word line. The failure detection circuit is connected to the other end of the word line and detects a voltage of the word line supplied with the one of the reading selection voltage and the reading non-selection voltage by comparing the voltage with a plurality of reference voltages.

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor chip is mounted onto a tab. In this case, since the entire surface of the silver plating on the suspending lead 1e is in a crushed state, it is possible to prevent contact of the semiconductor chip with the silver plating when mounting the chip onto the tab. Consequently, in a die bonding process, the semiconductor chip can slide on the tab without contacting the silver plating and thereby making it possible to diminish damage to the semiconductor chip when mounted onto the tab and hence to possibly prevent cracking or chipping of the chip when assembling the semiconductor device.