Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: The semiconductor device of the present invention includes a silicon substrate having a logic region and a RAM region, an NMOS transistor formed in the logic region, and an NMOS transistor formed in the RAM region. The NMOS transistor has a stack structure obtained by sequentially stacking the gate insulating film and the metal gate electrode over the silicon substrate. The NMOS transistor has a cap metal containing an element selected from a group consisting of lanthanum, ytterbium, magnesium, strontium, and erbium as a composition element between the silicon substrate and metal gate electrode. The cap metal is not formed in the NMOS transistor.

Abstract: An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

Abstract: The power supply apparatus realizes a high-speed response, a stable operation, and a low output ripple with low power consumption. The first stage switching regulator receives an input voltage and forms a first voltage. The second stage switching regulator receives the first voltage and forms a second voltage. The second stage switching regulator includes an N-phase (N is two or more) switching regulator, and the first voltage is set to be N times a target value of the second voltage. The input voltage is set to be higher than the first voltage.

Abstract: A semiconductor integrated circuit having a semiconductor chip mounted over a tape- or film-like substrate, the semiconductor integrated circuit having a higher strength against bending, as well as a method for manufacturing the semiconductor integrated circuit, are disclosed. The semiconductor integrated circuit comprises a bendable tape-like substrate, the tape-like substrate including external terminals, internal terminals provided for coupling to a rectangular semiconductor chip, and wiring lines for coupling the internal terminals and the external terminals with each other; and a reinforcing member for reinforcing the semiconductor chip over the tape-like substrate in a longitudinal direction of the semiconductor chip, the semiconductor chip and the reinforcing member being sealed with resin.

Abstract: A semiconductor device includes a substrate, an insulator layer on the substrate, an inductor on the insulator layer, and a film including a ferromagnetic particle on the inductor.

Abstract: A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region.

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.

Abstract: A semiconductor device includes: a first power source (PS1) pad supplied with a PS1 voltage; a PS1 line connected to the PS1 pad; a first ground line (G1); an output circuit operated using the PS1 voltage; a second power source (PS2) pad supplied with a PS2 voltage; a PS2 line connected to the PS2 pad; a second ground line (G2); a signal line connected to an output end of the output circuit; an input circuit connected to the signal line at an input end receiving a signal from the output end and operated using the PS2 voltage; a main protection circuit unit providing discharge routes between the PS1 pad and G1, G1 and G2, and G2 and the PS2 pad; and a sub protection circuit unit. The output circuit includes: a circuit element arranged between the PS1 line and the signal line and able to function as a resistive element.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop.

Abstract: In a method for producing a semiconductor device, two or more kinds of organic siloxane compound materials each having a cyclic SiO structure as a main skeleton and having different structures are mixed and thereafter vaporized. Alternatively, those two or more kinds of organic siloxane compound materials are mixed and vaporized simultaneously to produce a vaporized gas. Then, the vaporized gas is transported to a reaction furnace together with a carrier gas. Then, in the reaction furnace, a porous insulating layer is formed by the plasma CVD method or the plasma polymerization method using the vaporized gas.

Abstract: A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.

Abstract: Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A method for manufacturing a semiconductor device includes forming an electrode pad in a surface layer of an insulating layer; disposing a conductive particle, of which at least a portion of the surface is coated with a thermoplastic resin, over the electrode pad; and fixing the conductive particle over the electrode pad using the resin, by heating the resin to soften the resin, and then cooling and solidifying the resin after the conductive particle and the electrode pad are electrically connected to each other, to form the conductive particle as an external connection terminal.

Abstract: An N? layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N? layer, a trench isolation region is formed to surround the N? layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N? layer. Between trench isolation region and the N? layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N? layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

Abstract: A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit includes a first counter configured to receive a part of the plurality of input bits and to output a part of the plurality of output bits and a first signal, a control circuit configured to receive the clock signal and the first signal, and to output a second signal, and a second counter configured to receive another part of the plurality of input bits and the second signal, and to output another part of the plurality of output bits.