Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.

Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.

Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Abstract: An RF power amplifier device includes a driver stage amplifier, a first RF amplifier, a second RF amplifier and a DC voltage converter operated by first, second and third external power supply voltages. The output of the driver stage amplifier is supplied to the inputs of the first and second RF amplifiers. An effective device size of the first RF amplifier is set to a device size larger than that of the second RF amplifier. The third external power supply voltage is supplied to the DC voltage converter, so that the DC voltage converter generates a fourth operating power supply voltage corresponding to a low voltage and supplies it to an output terminal of the second RF amplifier. An output terminal of the first RF amplifier can be supplied with the second external power supply voltage without via the DC voltage converter.

Abstract: A power supply topology is used in which a transistor is provided on the side of an output node of a rectifying circuit. An inductor is provided on the side of a reference node, a resistor is inserted between the transistor and the inductor, and one end of the resistor is coupled to a ground power supply voltage of a PFC circuit. The PFC circuit includes a square circuit which squares a result of multiplication of an input voltage detection signal and feedback information (output voltage of an error amplifier circuit). The PFC circuit drives on the transistor when a detection voltage developed at the resistor reaches zero, and drives off the transistor when the detection signal reaches an output signal of the square circuit.

Abstract: A method for manufacturing a semiconductor device including a vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type.

Abstract: A magnetic random access memory which includes a magnetic record layer which is ferromagnetic; a ferromagnetic magnetization fixed layer whose magnetization is fixed; and a non-magnetic spacer layer provided between the magnetic record layer and the magnetization fixed layer.

Abstract: A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition.

Abstract: To fabricate a power MOSFET, etc. high in voltage-proofing (or breakdown voltage) and low in ON resistance (or On-state resistance) by a trench filling method, trial manufacture of power MOSFETs, etc. has been repeated with varying internal structures and layouts of super junction structures in a chip inner region located inside a guard ring. As a result, there occasionally occurred a source-drain voltage-proofing defect attributable to outer end portions of a supper junction structure. In one aspect of the present invention there is provided a semiconductor device having a power semiconductor element with a super junction structure introduced substantially throughout the whole surface of a drift region, the super junction structure being provided substantially throughout the whole surfaces of end portions of a semiconductor chip which configures the semiconductor device.

Abstract: According to the present invention, a small impedance detection circuit capable of accurately detecting the impedance of an object to be measured and an adjustment method of an impedance detection circuit can be provided. In the impedance detection circuit according to the present invention, an AC signal generator outputs an AC signal. A detection circuit, which is connected to a circuit to be measured, applies an AC signal to the circuit to be measured. Further, the detection circuit outputs a first signal corresponding to the composite impedance of the impedance of the circuit to be measured and a parasitic impedance. A correction circuit outputs a second signal in synchronization with the first signal. A subtraction circuit outputs a detection signal obtained by subtracting the second signal from the first signal.

Abstract: A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing.

Abstract: A semiconductor device includes a transistor having multiple trenches with the thickness thereof being intermittently changed in the lateral direction of a gate, a gate insulating film formed on the side walls and at the bottom of each of the trenches, a gate electrode formed over the gate insulating film, a source region formed in the surface of the substrate on one side in the longitudinal direction of the gate, and a drain region formed in the surface of the substrate on the other side in the longitudinal direction of the gate.

Abstract: Malfunction attributable to an induced electromotive force such as a back electromotive force or a regenerative braking force of an inductive load in a load driving device is prevented. When an on-state current flows in an output transistor, a second transistor applies a supply voltage applied to a source of the output transistor to a back gate of the first transistor. On the other hand, when a negative current flows in the output transistor in a direction opposite to that of the on-state current, the second transistor applies a supply voltage applied to a drain of the output transistor to the back gate of the first transistor.

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract: A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.

Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump exhausts the chamber. The radio frequency power supply supplies radio frequency power to the electrode through the conductive knitted wire mesh.

Abstract: An adaptive front-end architecture for a receiver is disclosed. In one embodiment, the adaptive front-end architecture includes an input configured to receive an input signal and a linear low-noise amplifier connected to the input and configured to amplify the input signal to produce an amplified input signal. The adaptive front-end architecture further includes a first passive mixer arrangement configured to generate first a local oscillator signal and mix the first local oscillator signal with the amplified input signal to produce a first baseband output signal. The adaptive front-end architecture further includes a second passive mixer arrangement configured to generate a second local oscillator signal and mix the second local oscillator signal with the input signal to produce a second baseband output signal. The adaptive front-end architecture further includes a baseband impedance component configured to filter the first baseband signal and/or the second baseband signal using impedance translation.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.