Patents Assigned to RENESAS
-
Publication number: 20110165520Abstract: A method of forming a pattern including a first pattern portion having a first minimum dimension and a second pattern portion having a second minimum dimension includes a first exposure step of performing exposure using a Levenson-type mask and a second exposure step of performing exposure using a half tone-type mask. When second minimum dimension is 1.3 time or more than the first minimum dimension, the exposure amount of the second exposure step is set to be equal to or smaller than the exposure amount of the first exposure step.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mitsuru OKUNO, Akemi Moniwa
-
Publication number: 20110163444Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.Type: ApplicationFiled: March 10, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Eiji HAYASHI
-
Publication number: 20110163425Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.Type: ApplicationFiled: March 10, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yasutaka NAKASHIBA
-
Publication number: 20110163401Abstract: Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Mikio TSUJIUCHI
-
Publication number: 20110165737Abstract: A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kenichi Yoda
-
Publication number: 20110164866Abstract: A ring-like region excluding a central region and a peripheral region from an image pickup area is preset as a focus area. An image signal is acquired through a lens and a CCD circuit. Based on the image signal thus acquired, a contrast value indicating the degree of in-focus of the preset focus area is calculated. A lens position corresponding to a maximum contrast value of the preset focus area is determined as an in-focus lens position. In autofocus processing, face detection is carried out first. Then, if the result of face detection is successful, a face region is set up as a focus area, and focus adjustment is performed based thereon. Alternatively, if the result of face detection is unsuccessful, focus adjustment is performed based on the preset focus area.Type: ApplicationFiled: January 4, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Norio KAYAMA, Yue SHEN
-
Publication number: 20110163438Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Noriyuki TAKAHASHI, Mamoru SHISHIDO
-
Publication number: 20110156225Abstract: A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 5 and 6 mounted on a main surface of a circuit board 1 are provided, the mount devices 5 and 6 are electrically connected to a wiring pattern 4 at the main surface of the circuit board 1, a sealant 7 of an insulating resin is formed to seal the mount devices 5 and 6, metal particles are applied to a surface of the sealant 7, and the metal particles applied are sintered, thereby forming an electromagnetic shielding layer 2, and electrically connecting the electromagnetic shielding layer 2 to a ground pattern 3 of the circuit board 1.Type: ApplicationFiled: July 31, 2009Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Hozoji, Toshiaki Morita, Yusuke Yasuda, Chiko Yorita, Yuji Shirai
-
Publication number: 20110156829Abstract: An oscillator combined circuit comprises: an oscillator including a resonance circuit that includes an inductor and capacitors, and a frequency divider that includes a differential pair that receives an oscillation output signal of the oscillator, and forms current paths from a power supply side, with first ends thereof on a side opposite to the first power supply being connected to the center tap of the inductor of the oscillator. The oscillator and the frequency divider are cascode-connected between ground and the power supply and a DC power supply current flowing from a DC supply current terminal of the frequency divider to a ground side is reused as a power supply current of the oscillator.Type: ApplicationFiled: December 27, 2010Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Jianqin WANG
-
Publication number: 20110156625Abstract: This invention provides a motor driving apparatus that made it possible to reduce torque ripples including those attributed to load variation of the motor and an associated method for control of motor revolution. An output stage to a multiphase DC motor is comprised of power elements to supply output voltages to multiphase coils and a predriver to supply drive voltages to the power elements. A resistor means detects a current flowing through the power elements. A supply current detector detects a voltage signal produced across the resistor means as a supply current, using a high-speed ADC and a moving average filter. An output controller generates a PWM signal with a frequency lower than the frequency of the high-speed ADC so that the current detected by the supply current detector conforms to a current signal indicating a motor revolving speed and transfers the PWM signal to the output stage.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Minoru KUROSAWA, Yasuhiko KOKAMI
-
Publication number: 20110157754Abstract: An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.Type: ApplicationFiled: March 4, 2011Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Takayuki Nagai
-
Publication number: 20110155578Abstract: An objective of this invention is to reliably form a plating film. The following two steps are sequentially conducted: step 101 of connecting a film-formation surface of a wafer 109 to a cathode electrode 107, making the film-formation surface inclined from the surface of a plating solution 103 and immersing the wafer 109 into the plating solution 103 with applying a first current between the cathode electrode 107 and an Cu anode electrode 105 disposed in the plating solution 103, and step 103 of, after immersing the film-formation surface in the plating solution 103, applying a second current between the cathode electrode 107 and the Cu anode electrode 105 to form a metal film on the film-formation surface by electrolytic plating. In step 101, the first current is controlled on the basis of an inclination angle between the liquid surface and the film-formation surface.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akira FURUYA, Yasuaki TSUCHIYA
-
Publication number: 20110161904Abstract: A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.Type: ApplicationFiled: December 23, 2010Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Keiichirou KONDOU, Hiroyuki TSUCHIYA
-
Publication number: 20110156108Abstract: An insulating cover film is formed over at least a portion of a gate electrode in the direction of the channel width. A diffusion layer is formed to a portion of a substrate situating at a device forming region, thereby forming a source and a drain of a transistor. An insulating layer is formed over the device forming region, over the gate electrode, and over the insulating cover film. A contact is formed to the insulating layer and connected to the diffusion layer. A silicide layer is formed over the gate electrode. A side wall is formed higher than the gate electrode in a region in which the insulating cover film is formed. Then, the contact faces a region of the gate electrode in which the insulating cover film is formed.Type: ApplicationFiled: December 27, 2010Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Satoru MURAMATSU
-
Publication number: 20110156219Abstract: A semiconductor device is disclosed which can prevent interlayer cracking of interlayer dielectric films while improving the adhesion between the interlayer dielectric films in a dicing process using a dicing blade. In a scribing line area, dummy wirings are formed respectively in a blade area through which a dicing blade passes in a dicing process and in non-blade areas formed on both sides of the blade area and through which the dicing blade does not pass. In the non-blade areas, vertically adjacent dummy wirings are coupled together through dummy vias, while in the blade area the vertically adjacent dummy wirings are not coupled together through dummy vias.Type: ApplicationFiled: December 23, 2010Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitsugu KAWASHIMA, Masayuki HIROI, Hirofumi SAITO
-
Publication number: 20110156164Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing at least a first impurity, and a second transistor formed in a logic region, and having a second source/drain region containing at least a second impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by an impurity and is deeper than the junction depth of the second source/drain region.Type: ApplicationFiled: February 11, 2011Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki Shirai
-
Publication number: 20110147815Abstract: Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.Type: ApplicationFiled: December 20, 2010Publication date: June 23, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiroshi TAKEDA
-
Publication number: 20110148844Abstract: A display panel driver including a compression circuit configured to, when receiving image data of a set of pixels of a target block, generate compressed image data corresponding to the target block by compressing the image data, the number of the set of pixels being equal to or more than four, an image memory configured to store the compressed image data, a decompression circuit configured to generate decompressed image data by decompressing the compressed image data reading from the image memory, and a drive circuit configured to drive a display panel in response to the decompressed image data, wherein the compression circuit selects one of a plurality of compression methods based on a correlation between the image data of the set of pixels of the target block, and generates the compressed image data by using the selected compression method.Type: ApplicationFiled: March 2, 2011Publication date: June 23, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hirobumi Furihata, Takashi Nose
-
Publication number: 20110148942Abstract: A display data correction apparatus is provided with: a control circuit responsive to an input gray-level value for initially providing first to N-th control points (N?3) defined in a coordinate system in which a first coordinate axis is associated with the input gray-level value and a second coordinate axis is associated with an output gray-level value to be calculated for the input gray-level value; and a processing circuit obtaining an output gray-level value by repeating an update operation in which the first to N-th control points are updated. The degree (N?1) Bezier curve is used as an approximated curve of the gamma curve. The output gray-level value is finally obtained as the coordinate value of a specific point in the degree (N?1) Bezier curve along the second coordinate axis, where the specific point has the coordinate value closest to the input gray-level value along the first coordinate axis.Type: ApplicationFiled: December 20, 2010Publication date: June 23, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hirobumi Furihata, Takashi Nose
-
Publication number: 20110147058Abstract: A multilayer wiring substrate has a configuration in which a first wiring layer including a plurality of first conductive members formed in a first insulating film, and formed to be exposed at a second surface side, and a second wiring layer including a plurality of second conductive members formed in a second insulating film which is formed on a first surface side on the side opposite to the second surface are laminated. The plurality of second conductive members is respectively connected directly to any of the plurality of first conductive members or connected through a different conductive material. The plurality of first conductive members is connected directly to any of the plurality of second conductive members or connected through a different conductive material, but includes dummy conductive members which do not form current pathways connecting with connected second conductive member.Type: ApplicationFiled: December 20, 2010Publication date: June 23, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masaya KAWANO, Koji SOEJIMA
