Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract: A semiconductor integrated circuit, includes a control flip-flop for inputting a scan control signal and a scan path chain formed of a plurality of scan storage elements serially connected to each other. The scan path chain performs a shift operation as a first mode when an output of the control flip-flop is a first status value, and performs a normal operation as a second mode when an output of the control flip-flop is a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching.

Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.

Abstract: An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate.

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA0, WLB0, WLB1, WLA1, WLA2, . . . . Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line as a criterion, while the word lines of different ports are disposed at the pitch d1 on the other. With the above configuration, for example, as compared with a case of alternately disposing WLA and WLB, interference between ports can be reduced even with a small area, and the noise margin can be expanded.

Abstract: Characteristics of a low-k insulating film grown on a substrate is modulated in the thickness-wise direction, by varying the ratio of high-frequency input and low-frequency input used for inducing plasma in the course of forming the film, to thereby improve the adhesion strength while keeping the dielectric constant at a low level, wherein the high-frequency input and the low-frequency input for inducing plasma are applied from a single electrode, while elevating the level of low-frequency input at least either at the start of formation or at the end of formation of the insulating film, as compared with the input level in the residual time zone, thereby the insulating film is formed to have a close-adhesion layer in at least either one of the end portions of the film in the thickness-wise direction, by the contribution of both of the high-frequency input and the low-frequency input, and to have a low-k insulating film in the residual portion of the film, by lowering or zeroing the level of the low-frequency i

Abstract: An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first differential signal interconnection, the second differential signal interconnection and the second voltage interconnection are arranged in this order. An interval between the first and second differential signal interconnections is longer than an interval between the first voltage interconnection and the first differential signal interconnection and is longer than an interval between the second differential signal interconnection and the second voltage interconnection.

Abstract: The present invention is directed to improve compression efficiency by variable-length coding in accordance with characteristics of image data to be processed. An apparatus for compressing quantized data by variable-length coding includes: a statistical information storing memory (212) for storing statistical information (MBTyp and CBPL) of coded image data; a variable-length code table generating unit (213) for generating a variable-length code table on the basis of the statistical information stored in the memory; and a variable-length coding unit (205) for performing variable-length coding on the basis of the variable-length code table.

Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.

Abstract: When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and second cache memories, a consistency management circuit for managing consistency of data stored in the first and second cache memories, a request signal line for transmitting a request signal for a data update request from the consistency management circuit to the first and second cache memories, an information signal line for transmitting an information signal for informing completion of the data update from the first and second cache memories to the consistency management circuit, and a cache power control circuit for controlling supply of a clock signal and power to the first and second cache memories in accordance with the request signal and the information signal.

Abstract: To suppress adhesion of impurities to a semiconductor light emitting element, there is provided a nitride-based semiconductor light emitting element including: a laminated body having a first cladding layer, an active layer formed over the first cladding layer, and a second cladding layer formed over the active layer; and a dielectric film with a thickness of 3 ?m or more that is formed on the side surface of the laminated body on the side where light is emitted and that covers at least a first side surface of the active layer.

Abstract: A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction.

Abstract: It is desired to effectively suppress breaking of a protection target circuit caused by direct application of an ESD surge voltage to the circuit. The semiconductor device includes: a VDD pad; a signal output pad; a GND pad; a high-potential power source line; a signal line; a low-potential power source line; main ESD protection elements; a PMOS transistor; and an output circuit. The output circuit includes: an NMOS transistor N1 whose source is connected to the signal line, and whose drain is connected to the low-potential power source line; and an NMOS transistor N2 connected between the gate of the NMOS transistor N1 and the low-potential power source line. The source of the PMOS transistor is connected to the signal line, the drain thereof is connected to the gate of the NMOS transistor N1, and the gate and back gate thereof are connected to the high-potential power source line.

Abstract: A source driver includes a dividing circuit, a start signal capturing unit, a pulse width determining unit and a control circuit. The dividing circuit produces a divided clock by dividing a basic clock signal. The start signal capturing unit captures the start signal at timing of the edge of the divided clock. The pulse width determining unit determines a pulse width of the start signal that is captured. The control circuit changes the timing to start capturing the data according to the pulse width of the start signal. With this structure, the latter source driver is able to adjust capturing timing to effective data timing input thereto, even though final data does not end at the falling edge of the divided clock signal.

Abstract: In a power supply unit having high-side and low-side switching elements each including power MOSFETs connected in parallel, the power MOSFETs are controlled so that the number of the transistors in an off state is increased as an output current becomes lower, and particularly, the transistors turned off when the output current is low are disposed on an outer side of a loop formed from a positive terminal of an input capacitor of a printed board to a negative terminal of the input capacitor via the switching elements. Thus, by turning off packages of the power MOSFETs disposed on an outer side of the main circuit loop and turning on packages of the power MOSFETs disposed on an inner side of the loop, the parasitic inductance of a main circuit is reduced, so that the switching loss can be reduced and efficiency in a light load can be improved.

Abstract: There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a work function control layer formed on the gate insulating film; a first silicide layer formed on the work function control layer; a polysilicon gate electrode formed on the first silicide layer; and a source region and a drain region formed on opposite sides of a region under the polysilicon gate electrode in the semiconductor substrate.

Abstract: A semiconductor integrated circuit free from increase in chip area or significant reversion in designing is provided. The semiconductor integrated circuit includes: IO buffers arrayed in line; pad coupling wirings respectively arrayed in correspondence with the IO buffers; and IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers, set in a layer different from those of the IO buffers and the pad coupling wirings so that they overlap with part of the corresponding pad coupling wirings, and extended to other pad coupling wirings adjacent to the corresponding pad coupling wirings. Each of the IO buffer switching wirings is formed in an identical shape so that it is not short-circuited to adjacent other IO buffer switching wirings. The IO buffers are electrically coupled with the corresponding IO buffer switching wirings in the same positions.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe, The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line.

Abstract: A solid-state image pickup device 1 includes a semiconductor substrate 10, light receiving unit 14 and light shielding film 20. The solid-state image pickup device 1 is back surface incident type and photoelectrically converts light indent on the back surface S2 of the semiconductor substrate 10 from an object into electrical charges and receives electrical charges produced by photoelectric conversion at the light receiving unit 14 to image the object. The light receiving unit 14 forms a PN junction diode with the semiconductor substrate 10. The light shielding film 20 is provided over a front surface S1 of the semiconductor substrate 10 so as to cover the light receiving unit 14. The light shielding film 20 serves to shield light incident on the front surface S1 from the outside of the solid-state image pickup device 1.