Abstract: A semiconductor circuit inhibiting the increase in the number of elements required to enable core circuit testing and a core test circuit enabling consecutive-pattern testing of a core circuit without increasing the number of terminals are provided. The semiconductor circuit includes a core circuit, a combinational circuit, a scan path for the combinational circuit with the scan path including cascaded scan flip-flops connected to input and output terminals of the combinational circuit, and scan path sharing circuits including multiplexers for allowing output signals of the core circuit to be inputted to the scan flip-flops, and allows a core circuit not included in the combinational circuit to be tested using the scan path for the combinational circuit. The core test circuit is provided with output shift registers for storing and outputting test results of plural test patterns outputted from output terminals of the core circuit to be eventually scanned out from the output shift registers.

Abstract: A method of forming a semiconductor device includes forming a dummy metal gate layer including work function metals directly on a base insulator, diffusing the work function metals into the base insulator by annealing, removing the dummy metal gate layer by a wet etching, forming a metal gate on the base insulator, and forming a high-k insulator on the metal gate.

Abstract: A bandgap voltage reference circuit is provided with: a feedback circuitry, first and second PN junction elements and first and second resistor elements. The feedback circuitry provides a feedback so as to reduce a voltage between first and second nodes. The first PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The second PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The first resistor element is connected between the first node and the first PN junction element, and a second resistor element is connected between the second node and the second PN junction element.

Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

Abstract: A semiconductor device according to the present invention includes a substrate, an IC chip that is fixed over the substrate, a conductor that is disposed over a surface of the substrate, a solder resist that covers the surface of the substrate and the conductor and includes an opening that exposes the conductor in a section corresponding to a fixed surface of the IC chip, and an adhesive that contacts an exposed part of the conductor, in which the exposed part is made by the opening.

Abstract: A multi-phase power source device capable of easily changing the number of phases is realized. For example, a plurality of drive units POL[1]-POL[4] corresponding to the number of phases are provided, wherein each POL[n] receives a phase input signal PHI[n] serving as a pulse signal, and generates a phase output signal PHO[n] by delaying PHI[n] by a predetermined cycles of a clock signal CLK. PHI[n] and PHO[n] of each POL[n] are coupled in a ring, wherein each POL[n] performs a switching operation with PHI[n] or PHO[n] as a starting point. In this case, each POL[n] charges and discharges a capacitor Cct commonly coupled to each POL[n] with an equal current, and a frequency of CLK is determined based on this charge and discharge rate. That is, if the number of phases increases n times, the frequency of CLK will be automatically controlled to n times.

Abstract: A semiconductor apparatus includes: a wiring board; a lid; and gap filling resin. A semiconductor chip is mounted on the wiring board. The lid includes inlet portions for injecting resin. The semiconductor chip is covered with the lid on the wiring board. The gap filling resin bonds the wiring board and the lid inside the lid.

Abstract: To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: A display panel drive circuit is provided with a first display output terminal to be connected with a data line of a display panel, first and second output stages, and a control circuit. The first output stage is directly connected with the first display output terminal and configured to output a data signal with the positive polarity with respect to a standard voltage level. The second output stage is also directly connected with the first display output terminal and configured to output a data signal with the negative polarity with respect to the standard voltage level. The control circuit controls the first and second output stages so that one of the first and second output stages is selectively activated while the other of the first and second output stages is deactivated.

Abstract: A screening apparatus includes: a measurement unit measuring characteristics of a semiconductor device and reading an identification code allocated to the semiconductor device; a database storing a table representing a correspondence between an identification code and a fabrication condition of a semiconductor device; a conversion unit extracting, based on the identification code sent from the measurement unit, a corresponding fabrication condition from the database and associating the extracted fabrication condition with the characteristics corresponding to the fabrication condition; a characteristics reconstruction unit classifying the characteristics according to the fabrication condition sent from the conversion unit; and an evaluation and analysis unit evaluating and analyzing the characteristics classified by the characteristics reconstruction unit according to the fabrication condition in a predetermined manner and determining a semiconductor device to be screened.

Abstract: A ?? analog-to-digital converter includes a previous stage amplifier circuit which amplifies an input signal, a conversion circuit which converts an analog signal into a digital signal, where the analog signal is output from the previous stage amplifier circuit, an input node provided in the previous stage amplifier circuit, a plurality of capacitors provided in the conversion circuit, a first amplifier and a second amplifier, and a path switching circuit which connects the first amplifier to the input node in a first mode and connects the first amplifier to the plurality of capacitors in a second mode, where the first mode is for sampling the analog signal and the second mode is for performing an integration operation. The first amplifier forms the previous stage amplifier circuit in the first mode, and forms an integrator which carries out the integration operation performed in the conversion circuit in the second mode.

Abstract: A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 ?m or more.

Abstract: A semiconductor device, includes a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, the first wiring layer containing a first via having a first aspect ratio and a first wire having a second aspect ratio, the first aspect ratio being equal to or larger than the second aspect ratio, and a second wiring layer overlying the first wiring layer, the second wiring layer containing a second via having a third aspect ratio and a second wire having a fourth aspect ratio, the third aspect ratio being smaller than the fourth aspect ratio.

Abstract: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.

Abstract: A semiconductor device includes an undoped InGaAs layer; an Si-doped GaAs layer formed thereover and equipped with a first recess portion; a two-layered semiconductor layer formed between the undoped InGaAs layer and the Si-doped GaAs layer, equipped with a second recess portion provided in the first recess portion, and composed of an undoped ordered InGaP layer and an undoped GaAs layer formed thereover; a C-doped GaAs layer provided over the undoped InGaAs layer in the second recess portion; and a sidewall insulating film provided between the C-doped GaAs layer and the interface between the undoped GaAs layer and the undoped ordered InGaP layer, but not provided at a portion between the undoped ordered InGaP layer and the C-doped GaAs layer.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.