Abstract: A motor driving apparatus includes a first driving control circuit (an MCU, a driving circuit, an input circuit, a power management IC) and a second driving control circuit (an MCU, a driving circuit, an input circuit, a power management IC). The first driving control circuit and the second driving control circuit are configured to drive a corresponding winding group of winding groups of a motor, and have a master mode for outputting a synchronous trigger signal in synchronization with driving of the corresponding winding group and a slave mode for synchronizing the driving of the corresponding winding group with an input synchronous trigger signal. When an error has occurred in an operation of the first driving control circuit in the master mode, the second driving control circuit switches an operation mode of the second driving control circuit from the slave mode to the master mode.

Abstract: A power feeding system according to one embodiment includes a negotiation controller included in a power receiving device, a negotiation controller included in a power feeding device, and a determination unit that determines whether to allow power feeding from the power feeding device to the power receiving device. The negotiation controller in the power receiving device includes an information acquisition unit that acquires information to be used for the determination regarding whether to allow the power feeding. The determination unit determines, using the information acquired in the information acquisition unit, whether to allow the power feeding from the power feeding device. The negotiation controller in the power feeding device controls the power supply to the power receiving device in accordance with the result of the determination in the determination unit. The determination unit is provided in at least one of the power feeding device and the power receiving device.

Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

Abstract: In a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate, dielectric breakdown of a gate insulating film is prevented and the polarization performance of the ferroelectric film is enhanced to improve the performance of a semiconductor device. In a memory cell including a field effect transistor including a control gate electrode formed over the semiconductor substrate, between the control gate electrode and a main surface of the semiconductor substrate, a paraelectric film and the ferroelectric film are formed by being stacked in this order over the main surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

Abstract: Provided are a motor angle detector for detecting a motor angle, a current detector for detecting a motor current value to drive a motor, a vehicle inclination angle detector for detecting a vehicle inclination angle, a motor control circuit for outputting a control signal to control the driving of the motor, and a storage apparatus. The storage apparatus stores data obtained by associating the motor current value, a setting value in the motor control circuit for outputting the control signal, the vehicle inclination angle, and the motor angle at a first time with each other, and the motor control circuit controls the driving of the motor on the basis of information of the motor current value and the vehicle inclination angle at a second time and the data at the first time.

Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

Abstract: A semiconductor device capable of lowering a temperature coefficient and increasing a sheet resistance value (?s value) and a manufacturing method thereof are provided. The resistive layer RL is made of polycrystalline silicon containing boron. The concentration distribution of boron in the thickness direction of the resistive layer RL includes a concentration peak PC and a low concentration portion LC having a concentration of boron lower than the concentration of boron in the concentration peak PC by two orders of magnitude or more.

Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.

Abstract: To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region.

Abstract: An improvement is achieved in the performance of a semiconductor device. A second component mounting portion over which a first electronic component is mounted is connected to a coupling portion of a lead frame via a suspension lead. The suspension lead has a first portion between the second component mounting portion and the coupling portion and a second portion between the first portion and the coupling portion. The second portion has a third portion connected to the first portion and having a width smaller than a width of the first portion, a fourth portion connected to the first portion and having a width smaller than the width of the first portion, and a through hole (opening) located between the third and fourth portions. Each of the first, third, and fourth portions has the same thickness. After a sealing body is formed, a cutting jig is pressed against the suspension lead to cut the suspension lead.

Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

Abstract: An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.

Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.

Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.

Abstract: A cache memory device includes: data memory that stores cache data corresponding to data in main memory; tag memory that stores tag information to identify the cache data; an address estimation unit that estimates a look-ahead address to be accessed next; a cache hit determination unit that performs cache hit determination on the look-ahead address, based on the stored tag information; and an access controller that accesses the data memory or the main memory based on the retained cache hit determination result in response to a next access.

Abstract: Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70. In the step (d), at least one of the electrode surface 31 and the electrode surface 41 is exposed from the sealing body 70 by irradiating at least one of the front surface and the back surface of the sealing body 70 with the laser 110.