Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.

Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.

Abstract: One or more embodiments relate to a control circuit for an input filter circuit in a switch mode power supply comprising a power switch and a switch controller to control the power switch to provide a regulated output voltage and current to a load. The control circuit, also referred to as a filter control circuit, can be used to detect a high voltage surge at its input and disconnect a capacitor in the input filter circuit from an input return, thereby protecting the input filter capacitor and the SMPS from damage. According to certain aspects, the control circuit can be integrated with the switch controller. Additionally, the control circuit can provide power to the switch controller at start-up.

Abstract: The semiconductor device includes a plurality of cores, a sensor for detecting a temperature, and a control circuit configured to obtain each power consumption of the respective cores so as to select the core as a control object in accordance with the obtained power consumption.

Abstract: To provide a power supplying control apparatus, a power supplying apparatus, and a power supplying control method which control power supply appropriately. A power supplying apparatus according to the present embodiment is equipped with a plurality of ports corresponding to a USB (Universal Serial Bus) PD (Power Delivery) standard, a plurality of electric power supplying circuits which are provided corresponding to the ports and supply power to power receiving devices coupled to the ports, and a controller which holds a table of power profiles to which power receiving capabilities for each power receiving device are set, and controls the electric power supplying circuits, based on the table in such a manner that total supply power supplied from the electric power supplying circuits does not exceed a prescribed value.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

Abstract: Power consumption of a semiconductor device is reduced. A semiconductor device according to an embodiment includes a plurality of circuits, a bus circuit including a plurality of buffers that temporarily store communication data between the circuits and a plurality of arbitration circuits that arbitrate an access between the circuits and the buffers, a storage unit that stores information based on a use state of the buffers during communication between the circuits and configuration information including designation of unused circuits that are not used for the communication from among the circuits, and a control circuit that controls the bus circuit so as to stop use of unused buffers that are not used for the communication from among the buffers and at least a partial configuration in arbitration circuits corresponding to the unused circuits from among the arbitration circuits based on the configuration information.

Abstract: One or more of the present embodiments allows multiple controllers to be automatically configured as a single or multi-rail voltage regulator system using a local bus that can communicate between controllers with a minimal set of pinstraps. This allows the system to be configured with a reduced set of configuration pins and without the need for stored configurations in the controller's own memory or configurations performed by an external host.

Abstract: In order to quickly and reliably establish link up, when a communication device detects power on or link down, an idle signal generation circuit generates an idle signal. Then, an I/F circuit transmits the idle signal to a communication device which is a communication partner through a selection circuit. Further, the I/F circuit transmits and receives learning signals to and from the communication device which is a communication partner. A Step 1 learning circuit, a Step 2 learning circuit, and a Step 3 learning circuit establish link up by using the learning signals. When not receiving a signal from a link detection circuit indicating that link up is established, a reset mask circuit transmits a reset signal generated by a reset signal generation circuit, to the Step 1 learning circuit, the Step 2 learning circuit, and the Step 3 learning circuit to allow them to learn again.

Abstract: The conventional semiconductor device requires use of a separate vibration sensor or the like to detect a rotation abnormality of a motor. According to an embodiment, a semiconductor device includes: a resolver rotation angle conversion circuit that obtains a rotation angle signal indicative of a rotation angle of the motor obtained from a resolver that measures the rotation angle of the motor and generates rotation angle information by converting the rotation angle signal to a digital value; a motor rotation angle conversion circuit that generates rotation angle temporal change information by converting the rotation angle information with respect to each phase of the motor to an angular change of the motor; and a determination circuit that determines that an abnormality occurs in the motor in a case of exceeding a fluctuation abnormality detection range of the rotation angle temporal change in the rotation angle temporal change information.

Abstract: A rotation angle correction device corrects a rotation angle of a converter converting a signal from a resolver attached to a motor. An arrival time measurement unit measures an arrival time at which the rotation angle reaches a specified rotation angle from a reference angle in a current cycle. A reference time calculation unit calculates a reference time at which the rotation angle reaches the specified rotation angle from the reference angle assuming that the motor rotates in the current cycle at the same angular velocity as an angular velocity in a previous cycle. A difference calculation unit calculates a difference between the arrival time and the reference time. An error angle calculation unit multiplies the difference between the arrival time and the reference time and the angular velocity in the previous cycle to obtain an error angle. A correction unit corrects the rotation angle based on the error angle.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

Abstract: A semiconductor device includes a bypass wiring connected with a first through via and a second through via, on a second surface side of a semiconductor substrate that is an opposite side of a wiring structure formed on a first surface side of the semiconductor substrate.

Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.

Abstract: A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.

Abstract: In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.

Abstract: A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a direct memory access controller (DMAC). In one embodiment, the method includes calling a function stored in the flash memory, wherein a first parameter is passed to the function when it is called, wherein the first parameter identifies a first data structure that is stored in flash memory, and wherein the first data structure includes first DMAC control values. The CPU reads the first DMAC control values in response to the CPU executing instructions of the function. The CPU then writes the first DMAC control values to respective control registers of the DMAC in response to the CPU executing instructions of the function.

Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.