Abstract: A semiconductor device is provided that can process various events while suppressing complication of logical configuration. The semiconductor device includes a central processing unit, a plurality of functional blocks, and an event controller. Each functional block includes an interrupt factor detection unit that detects an interrupt factor and outputs an event processing request based on the interrupt factor, an event ID input unit that receives an input of an event ID outputted from the event controller, an event response specification unit that determines whether or not the inputted event ID is an event ID that requires response and, when the inputted event ID is an event ID that requires response, specifies response content corresponding to the inputted event ID, and an event response processing unit that performs event response processing based on the specified response content.

Abstract: In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.

Abstract: An on-vehicle communication device has a communication unit which communicates with a roadside device, a roadside device position information storage unit which stores in advance first position information indicating a position of the roadside device, a vehicle position information acquisition unit which acquires second position information indicating a position of the vehicle, an approach decision unit which decides whether the vehicle approaches the roadside device on the basis of the first position information stored in the roadside device position information storage unit and the second position information that the vehicle position information acquisition unit acquires and a communication control unit which switches a state of the communication unit from a power-saving state to a non-power-saving state in a case where the approach decision unit decides that the vehicle approaches the roadside device.

Abstract: An operating condition is controlled from viewpoints both processing capacity and power consumption. A CPU 11 includes, for example, a plurality of CPU cores 11a to 11d, and configured to such that an operating condition can be varied. A performance table 26 is a table representing a relationship between the operating condition of the CPU 11 and the processing capacity of the CPU 11. A power consumption table 27 is a table representing a relationship between the operating condition of the CPU 11 and power consumption. An operation control unit 22 controls the operating condition of the CPU 11 referring to the performance table 26 and the power consumption table 27.

Abstract: Provided is a semiconductor device including: an AC voltage generation unit that generates an AC voltage having an amplitude according to a control signal; a resistance element provided in series with a measurement target, the AC voltage being applied to the resistance element; a voltage detecting unit that detects that a difference voltage between two ends of the resistance element has reached a specified voltage; and a control unit that outputs the control signal to the AC voltage generation unit to cause the AC voltage generation unit to generate the AC voltage so that the difference voltage reaches the specified voltage, based on a detection result of the voltage detecting unit.

Abstract: Error notification by a bus master for a speculative access and error notification by a bus slave for a non-speculative access are achieved while a circuit scale of the bus master is suppressed. A bus request includes mode information for selecting that error notification for an access is performed by the bus slave or the bus master. In a case where the mode information indicating that error notification is performed by the bus slave is included in the bus request, when an error for an access in that bus request has occurred, the bus slave performs error notification. In a case where execution of an instruction of a speculative load access has been fixed and error information for the load access has been received from the bus slave, the bus master performs error notification based on the error information.

Abstract: The present embodiments provide a region of a semiconductor device comprising a plurality of power transistor cells configured as trench MOSFETs in a semiconductor substrate. At least one active power transistor cell further includes a trenched source region wherein a trench bottom surface of the trenched source contact is covered with an insulation layer and layer of a conductive material on top of the insulation layer, to function as an integrated pseudo Schottky barrier diode in the active power transistor cell.

Abstract: The present disclosure provides a technique of suppressing competition of processes in a semiconductor device employing a multilayer bus configuration. A semiconductor device employing a multilayer bus configuration includes a control device controlling an access from each of bus maters to each memory, and a storage device for storing a corresponding relation between identification information identifying a storage region included in each memory and a group to which the storage region belongs.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: An oil-pump motor drive apparatus includes a current detection unit for detecting each of multi-phase currents flowing through coils of a stator, a control unit for converting the detected multi-phase currents into a d-axis current Id and a q-axis current Iq, calculating a phase error between an actual rotational position of the rotor and an imaginary rotational position by comparing the d-axis current Id with a d-axis current command value Idref and comparing the q-axis current Iq with the d-axis current command value Idref, performing control so that the phase error gets closer to zero, and outputting voltage command values indicating voltages to be applied to respective phases of the brushless motor, to a motor drive circuit, in which the control unit sets the d-axis current command value Idref to a value larger than zero when the number of revolutions of the motor is smaller than a predetermined number.

Abstract: A substrate including an insulating layer, a semiconductor layer, and an insulating film stacked on a semiconductor substrate and having a trench filled with an element isolation portion is provided. After removal of the insulating film from a bulk region by a first dry etching, the semiconductor layer is removed from the bulk region by a second dry etching. Then, the insulating film in an SOI region and the insulating layer in the bulk region are removed. A gas containing a fluorocarbon gas is used for first dry etching. The etching thickness of the element isolation portion by a first dry etching is at least equal to the sum of the thicknesses of the insulating film just before starting the first dry etching and the semiconductor layer just before starting the first dry etching. After first dry etching and before second dry etching, oxygen plasma treatment is performed.

Abstract: A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.

Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

Abstract: A semiconductor device includes a voltage measurement unit that measures an output voltage of a battery, a current measurement unit that measures a discharge current of the battery; and a controller that determines, in a first measurement mode, whether to employ a first discharge current as a power calculation current based on a difference between the first and a second discharge current, the second discharge current being the discharge current measured by the current measurement unit before the first discharge current is measured, in which the controller estimates an internal resistance of the battery based on the power calculation current and the output voltage measured in the first measurement mode and the discharge current and the output voltage measured in a second measurement mode, and calculates, based on the internal resistance that is estimated, a maximum power amount that can be output by the battery in the second measurement mode.

Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.

Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.

Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

Abstract: Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.