Patents Assigned to RENESAS
  • Pulsimeter, frequency analysis device, and pulse measurement method
    Patent number: 10568581
    Abstract: An object of the invention is to shorten a measurement time while preventing deterioration in resolution during frequency analysis and preventing a reduction in measurement range. A pulsimeter (1) includes a pulse data acquisition unit (100), a replication unit (16), and a frequency analysis unit (17). The replication unit (16) generates, when the number of pieces of acquired sampling data for a pulse rate calculation reaches n, m pieces of sampling data using the n pieces of sampling data and data obtained by replicating n-th sampling data. The frequency analysis unit (17) performs a frequency analysis on the m pieces of sampling data.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 25, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akane Hiroshima, Naoya Tokimoto, Yuji Shimizu
  • Electronic device
    Patent number: 10566879
    Abstract: A first semiconductor device having a power transistor for switching is mounted on a power wiring substrate PB1; a semiconductor device PKG6 having a driving circuit for driving the first semiconductor device and a semiconductor device PKG5 having a control circuit for controlling the semiconductor device PKG6 are mounted on a first principal surface of a control wiring substrate PB2; and a semiconductor device PKG4 having a regulator circuit is mounted on a second principal surface of the control wiring substrate PB2. On the first principal surface of the control wiring substrate PB2, the semiconductor device PKG5 and the semiconductor device PKG6 are mounted in a second area out of the second area and a third area adjacent to each other via a first area in which a plurality of holes HC3 are arranged.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Nishizono, Tadashi Shimizu, Tomohiro Nishiyama, Norikazu Motohashi
  • Semiconductor device and a manufacturing method thereof
    Patent number: 10566367
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Semiconductor device having multiport memory
    Patent number: 10566047
    Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
  • Method of manufacturing semiconductor device
    Patent number: 10566255
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Semiconductor device having data signal path of meandering shape via a plurality of wirings
    Patent number: 10566329
    Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Method of manufacturing semiconductor device and the semiconductor device
    Patent number: 10566183
    Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Ide
  • Method of packaging power semiconductor module including power transistors
    Patent number: 10566258
    Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kuniharu Muto, Koji Bando
  • Semiconductor storage device and method for controlling semiconductor storage device
    Patent number: 10566068
    Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoji Kashihara
  • Solid state image sensor and manufacturing method thereof
    Patent number: 10566373
    Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yotaro Goto, Tatsuya Kunikiyo, Hidenori Sato
  • Manufacturing method of semiconductor device
    Patent number: 10559595
    Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Semiconductor device and trace data storing method
    Patent number: 10558600
    Abstract: The present invention enables an unaligned access of a DMA controller to be dealt at the time of obtaining trace data. A DMA controller receives a DMA request and accesses a memory via a bus on a predetermined access unit basis in accordance with the received DMA request. When the DMA request indicates “read”, a trace interface outputs the data obtained from the memory by the DMA controller, a start address designated by the DMA request, and valid transfer size in the data obtained from the memory to a trace circuit. The trace circuit stores data of the amount of the valid transfer size from the start address designated by the DMA request in the data obtained from the memory into the trace buffer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichi Kuwabara, Takuya Mitsuhashi
  • Semiconductor device
    Patent number: 10558379
    Abstract: A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshikazu Sato, Haruhiko Matsumi
  • Method for manufacturing image capturing device and image capturing device
    Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Semiconductor device
    Patent number: 10559581
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Yamashita, Tamotsu Ogata, Masamichi Fujito, Tomoya Saito
  • Method of manufacturing a semiconductor device with wider sidewall spacer for a high voltage MISFET
    Patent number: 10559500
    Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Maekawa, Tatsuyoshi Mihara
  • Semiconductor device and memory module
    Patent number: 10552261
    Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Hashizume, Naoya Fujita, Shunya Nagata, Yoshisato Yokoyama, Katsumi Shinbo, Kouji Satou
  • Eye opening degree detection system, doze detection system, automatic shutter system, eye opening degree detection method, and eye opening degree detection program
    Patent number: 10552693
    Abstract: An object of the present invention is to provide an eye opening degree detection system that can accurately and stably calculate an eye opening degree. The eye opening degree detection system includes imaging devices that generate images including regions of both eyes, a one eye opening degree calculation unit that calculates each one eye opening degree of the left and right eyes of a first image, an eye opening degree selection unit that selects a correctly-calculated one eye opening degree, an eye opening degree calculation unit that calculates an eye opening degree on the basis of the one eye opening degree and an eye opening degree determination unit that compares the eye opening degree calculated on the basis of the first image with an eye opening degree calculated on the basis of a second image prior to the first image to determine the propriety of the eye opening degree.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: February 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuki Mori
  • Data processing device
    Patent number: 10552149
    Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: February 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sugako Ohtani, Hiroyuki Kondo
  • Method of manufacturing semiconductor device
    Patent number: 10551432
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi