Patents Assigned to Research Corporation
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Patent number: 12087557Abstract: A substrate processing system includes a processing chamber including a dielectric window and a substrate support arranged therein to support a substrate. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A Faraday shield is arranged between the coil and the dielectric window. An RF generator is configured to supply RF power to the coil. The coil is coupled by stray capacitance and/or directly coupled to the Faraday shield. A capacitor is connected to one of the coil and the Faraday shield to adjust a position of a voltage standing wave along the coil.Type: GrantFiled: September 10, 2020Date of Patent: September 10, 2024Assignee: LAM RESEARCH CORPORATIONInventors: Shen Peng, Tamarak Pandhumsoporn, Anthony Nguyen, Dan Marohl
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Patent number: 12087573Abstract: Methods and apparatuses are provided herein for oxidizing an annular edge region of a substrate. A method may include providing the substrate to a substrate holder in a semiconductor processing chamber, the semiconductor processing chamber having a showerbead positioned above the substrate holder, and simultaneously flowing, while the substrate is supported by the substrate holder, (a) an oxidizing gas around a periphery of the substrate and (b) an inert gas that does not include oxygen through the showerhead and onto the substrate, thereby creating an annular gas region over an annular edge region of the substrate and an interior gas region over on an interior region of the substrate; the simultaneous flowing is not during a deposition of a material onto the substrate, and the annular gas region has an oxidization rate higher than the interior gas region.Type: GrantFiled: July 9, 2020Date of Patent: September 10, 2024Assignee: Lam Research CorporationInventors: Gerald Joseph Brady, Kevin M. McLaughlin, Pratik Sankhe, Bart J. van Schravendijk, Shriram Vasant Bapat
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Patent number: 12087572Abstract: Disclosed are methods for the formation of silicon nitride (SiN) on only the horizontal surfaces of structures such as 3D NAND staircase. This allows for thicker landing pads for subsequently formed vias. In some embodiments, the methods involve deposition of a SiN layer over a staircase followed by a treatment to selectively densify the SiN layer on the horizontal surfaces with respect to the sidewall surfaces. A wet etch is then performed to remove SiN from the sidewall surfaces. The selective treatment results in significantly different wet etch rates (WERs) between the horizontal surfaces and the sidewalls.Type: GrantFiled: March 26, 2020Date of Patent: September 10, 2024Assignee: Lam Research CorporationInventors: Bart J. van Schravendijk, Soumana Hamma, Kai-Lin Ou, Ming Li, Malay Milan Samantaray
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Patent number: 12081180Abstract: A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion ?Vin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.Type: GrantFiled: October 10, 2022Date of Patent: September 3, 2024Assignee: Georgia Tech Research CorporationInventors: Edgar Felipe Garay, Hua Wang
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Patent number: 12077859Abstract: Methods and apparatuses for depositing approximately equal thicknesses of a material on at least two substrates concurrently processed in separate stations of a multi-station deposition apparatus are provided.Type: GrantFiled: January 28, 2022Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Ishtak Karim, Kiyong Cho, Adrien LaVoie, Jaswinder Guliani, Purushottam Kumar, Jun Qian
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Patent number: 12080626Abstract: A system for providing direct silicon microfluidic cooling for electronics includes a cooling block with a first side and a second side. A plurality of micro-pin fins are disposed on the first side of the cooling block. A thermal interface material layer contacts a second side of the cooling block while a manifold is coupled to the cooling block and faces the micro-pin fins. The manifold has an inlet port and an outlet port for supporting cooling fluid flow between the inlet port and outlet port. The cooling fluid from the inlet port and outlet port also flows between the micro-pin fins for removing heat from the micro-pin fins absorbed by the cooling block from the thermal interface layer. The inlet port and outlet port each further comprise a cooling block port having a first geometry that corresponds with edges of a second geometry formed by the micro-pin fins.Type: GrantFiled: February 13, 2020Date of Patent: September 3, 2024Assignee: Georgia Tech Research CorporationInventors: Luis Daniel Lorenzini Gutierrez, Yogendra Joshi
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Patent number: 12080528Abstract: Systems and methods for cleaning a showerhead are described. One of the systems includes a support section and a press plate located above the support section to be supported by the support section. The system further includes a cleaning layer located above the press plate. The cleaning layer moves to clean a showerhead. The support section contacts an arm of a spindle assembly for movement with movement of the arm.Type: GrantFiled: October 20, 2020Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Eric Bramwell Britcher, Gerald Vartanian
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Patent number: 12077858Abstract: Described herein are methods of filling features with tungsten and related apparatus. The methods described herein involve deposition of a tungsten nucleation layer prior to deposition of a bulk layer. The methods involve multiple atomic layer deposition (ALD) cycles. According to various embodiments, both a boron-containing reducing agent and silicon-reducing agent may be pulses during a single cycle to react with a tungsten-containing precursor and form a tungsten film.Type: GrantFiled: August 10, 2020Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Pragna Nannapaneni, Novy Tjokro, Sema Ermez, Ruopeng Deng, Tianhua Yu, Xiaolan Ba, Sanjay Gopinath
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Patent number: 12080592Abstract: Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.Type: GrantFiled: September 10, 2019Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Hui-Jung Wu, Bart J. van Schravendijk, Mark Naoshi Kawaguchi, Gereng Gunawan, Jay E. Uglow, Nagraj Shankar, Gowri Channa Kamarthy, Kevin M. McLaughlin, Ananda K. Banerji, Jialing Yang, John Hoang, Aaron Lynn Routzahn, Nathan Musselwhite, Meihua Shen, Thorsten Bernd Lill, Hao Chi, Nicholas Dominic Altieri
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Patent number: 12077862Abstract: An electrical connector includes first, second, third, and fourth electrical conductors. The first, second, third, and fourth electrical conductors each include a first end to be electrically connected to a respective electrically conductive pad formed on a surface of a ceramic layer of a substrate support and a second end to be electrically connected to a respective wire within a through hole in the substrate support. The electrical connector also includes a retainer to hold the first, second, third, and fourth electrical conductors in place.Type: GrantFiled: November 3, 2020Date of Patent: September 3, 2024Assignee: LAM RESEARCH CORPORATIONInventors: Siyuan Tian, Donald J. Miller
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Patent number: 12080562Abstract: A method for selectively etching a stack with respect to a mask is provided. An atomic layer etch is provided to at least partially etch the stack, wherein the atomic layer etch forms at least some residue. An ion beam is provided to etch the stack, wherein the ion beam etch removes at least some of the residue from the atomic layer etch.Type: GrantFiled: September 9, 2020Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Samantha Siamhwa Tan, Tamal Mukherjee, Wenbing Yang, Girish Dixit, Yang Pan
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Patent number: 12080518Abstract: An impedance match is described. The impedance match includes a housing having a bottom portion and a top portion. The bottom portion has match components and the top portion has an elongated body. A low frequency input is connected through the bottom portion of the housing, and the low frequency input is interconnected to a first set of capacitors and inductors. A high frequency input is connected through the bottom portion of the housing, and the high frequency input is interconnected to a second set of capacitors and inductors. An elongated strap extends between the bottom portion and the top portion of the housing. A lower portion of the elongated strap is coupled to the second set of capacitors and inductors and an upper portion of the elongated strap is connected to an RF rod at an end of the elongated body.Type: GrantFiled: January 12, 2021Date of Patent: September 3, 2024Assignee: Lam Research CorporationInventors: Felix Leib Kozakevich, Alexei Marakhtanov, Bing Ji, Ranadeep Bhowmick, John Holland
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Patent number: 12074039Abstract: A substrate processing system includes a hinge assembly configured to allow a substrate support and an RF bias assembly to slide, from a docked position to an undocked position, relative to other components of a processing chamber. A make-break connector is configured to supply fluid to at least one of the substrate support and the RF bias assembly. The make-break connector includes a first portion including a first fluid passage connected to a first conduit. A second portion includes a second fluid passage connected to a second conduit. The first fluid passage in the first portion fluidly communicates with the second fluid passage in the second portion. The first portion is configured to slide with the substrate support and the RF bias assembly relative to the second portion and the other portions of the processing chamber. The first portion is located inwardly relative to the second portion.Type: GrantFiled: February 25, 2021Date of Patent: August 27, 2024Assignee: LAM RESEARCH CORPORATIONInventor: Alexander Charles Marcacci
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Patent number: 12074049Abstract: A substrate support for a substrate processing chamber includes a baseplate, a ceramic layer bonded to the baseplate, and a seal provided in an outer perimeter of an interface between the ceramic layer and the baseplate. The seal is arranged to seal the interface from the substrate processing chamber and includes an adhesive comprising a first material arranged in the outer perimeter of the interface between the ceramic layer and the baseplate and a ring arranged in the outer perimeter of the interface between the ceramic layer and the baseplate. The ring is removable and comprises a second material having a greater resistance to plasma erosion than the first material.Type: GrantFiled: June 25, 2019Date of Patent: August 27, 2024Assignee: Lam Research CorporationInventor: Eric A. Pape
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Patent number: 12072689Abstract: For etching tools, a neural network model is trained to predict optimum scheduling parameter values. The model is trained using data collected from preventive maintenance operations, recipe times, and wafer-less auto clean times as inputs. The model is used to capture underlying relationships between scheduling parameter values and various wafer processing scenarios to make predictions. Additionally, in tools used for multiple parallel material deposition processes, a nested neural network based model is trained using machine learning. The model is initially designed and trained offline using simulated data and then trained online using real tool data for predicting wafer routing path and scheduling. The model improves accuracy of scheduler pacing and achieves highest tool/fleet utilization, shortest wait times, and fastest throughput.Type: GrantFiled: March 24, 2020Date of Patent: August 27, 2024Assignee: LAM RESEARCH CORPORATIONInventors: Raymond Chau, Chung-Ho Huang, Henry Chan, Vincent Wong, Yu Ding, Ngoc-Diep Nguyen, Gerramine Manuguid
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Patent number: 12072318Abstract: An apparatus for measuring contaminants on a surface of a component is provided. An extraction vessel for holding a measurement fluid has an opening adapted to form a meniscus using the measurement fluid. An actuator moves at least one of the extraction vessel and the component to a position where the meniscus is in contact with the surface of the component. A transducer is positioned to provide acoustic energy to the measurement fluid.Type: GrantFiled: May 19, 2020Date of Patent: August 27, 2024Assignee: Lam Research CorporationInventors: Amir A. Yasseri, Duane Outka, Armen Avoyan, Kennet Cresencio Baylon, John Daugherty, Girish M. Hundi, Cliff La Croix
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Patent number: 12073224Abstract: A substrate processing system comprises a module to perform an operation associated with processing a semiconductor substrate in the substrate processing system. The module includes a component used with the processing of the semiconductor substrate, and a file stored in the module. The file includes information about the component of the module. The substrate processing system comprises a controller to communicate with the module via a network of the substrate processing system. The controller receives the file from the module via the network, reads the information about the component from the received file, and maps, based on the information read from the received file, the component of the module to an option in an application used to configure the module. The controller automatically configures the component of the module using the option in the application to which the component of the module is mapped.Type: GrantFiled: November 13, 2020Date of Patent: August 27, 2024Assignee: LAM RESEARCH CORPORATIONInventors: Bridget Hill, Scott Baldwin, Thomas A. Stubblebine, Rainer Unterguggenberger, Raymond Chau
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Microneedle particles, compositions, and methods of treatment and delivering a substance of interest
Patent number: 12070567Abstract: Provided herein are microneedle particles, compositions that include microneedle particles, methods of treating skin, and methods of delivering a substance of interest. The microneedle particles may include one or more microneedles, and the microneedle particles may be configured to prevent the entire microneedle particle from penetrating the biological tissue. The microneedle particles may be dispersed in a liquid medium to form a composition. A biological tissue may be contacted with the microneedle particles to pre-treat the biological tissue, and a substance of interest may be applied to the pre-treated biological tissue.Type: GrantFiled: April 4, 2022Date of Patent: August 27, 2024Assignee: Georgia Tech Research CorporationInventors: Andrew Tadros, Mark R. Prausnitz -
Patent number: 12074029Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.Type: GrantFiled: July 21, 2022Date of Patent: August 27, 2024Assignee: Lam Research CorporationInventors: Patrick A. Van Cleemput, Shruti Vivek Thombare, Michal Danek
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Patent number: 12071689Abstract: A substrate processing system is provided and includes a substrate support, a memory, and calibration, operating parameter, and solving modules. The substrate support supports a substrate and includes temperature control elements. The memory stores, for the temperature control elements, temperature calibration values and sensitivity calibration values. The calibration module, during calibration of the temperature control elements, performs a first calibration process to determine the temperature calibration values or a second calibration process to determine the sensitivity calibration values. The sensitivity calibration values relate at least one of trim amounts or deposition amounts to temperature changes. The operating parameter module determines operating parameters for the temperature control elements based on the temperature and sensitivity calibration values.Type: GrantFiled: February 12, 2020Date of Patent: August 27, 2024Assignee: Lam Research CorporationInventors: Ramesh Chandrasekharan, Michael Philip Roberts, Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Nuoya Yang, Chan Myae Myae Soe, Ashish Saurabh