Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

Abstract: A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.

Abstract: Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Abstract: A system that includes a machine learning model that is configured to receive an input layout file that includes a portion of an integrated circuit layout that has a previously identified wafer hotspot, match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types, and output a proposed layout modification associated with the matching category of wafer hotspot types.

Abstract: Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.

Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.

Abstract: The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the selected word line is at an elevated risk for read failure. In response to the controller making a determination that the plane containing the selected word line is at an elevated risk for read failure, the controller is configured to conduct a post write read operation at least one word line of the plurality of word lines.

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

Abstract: An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

Abstract: A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.

Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.