Abstract: A DC-DC converter according to one or more embodiments is disclosed that may include: a drive voltage switching circuit of a drive circuit that drives a synchronous rectification MOS transistor. The drive voltage switching circuit may switch a connection so that the drive circuit supplies power from the output voltage to the drive circuit in response to the drive voltage for supplying power to the drive circuit being set to be lower than the output voltage. The drive voltage switching circuit may switch a connection so that the drive circuit supplies power from the drive voltage in response to the drive voltage for supplying power to the drive circuit being set to be higher than the output voltage.

Abstract: An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

Abstract: One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

Abstract: An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.

Abstract: An analog-digital conversion circuit is disclosed for comparing a comparison potential with a reference potential generated based on a reference power supply to convert a comparison potential to a digital value. An analog-to-digital converter generates the comparison potential based on a sampled and held input potential, the digital value, and the reference power supply. A current amount control unit controls current amount flowing to the current amount control element in each bit circuit. In response to second switches of the bit circuits being turned on in order from the upper bit in each bit circuit by the digital value, the current amount control unit applies a current control potential to the current amount control element in any of the bit circuits that the noise current is more than allowable value while the noise current proportional to the charge flowing from the capacitor is more than the allowable value.

Abstract: A semiconductor device is disclosed including a sub-layer with first conductivity type, a drift layer with first conductivity type, a base region with second conductivity type positioned on the drift layer, a source region in contact with the base region, a source electrode, a plurality of trenches, at least one of the trenches in contact with the drift layer, the base region, and the source region, a plurality of insulating regions, at least one of the insulating regions positioned inside of each trench, a plurality of gate electrodes, at least one of the gate electrodes positioned inside of each trench; and a plurality of field plates, at least one of the field plates electrically connected to the source electrode and positioned in the insulating region in the trench. The field plate comprises high-resistance polysilicon.

Abstract: A light emitting device (1) includes: three or more light emitting units (10, 20, 30) that individually include blue light emitting element, a wavelength range of the blue light emitting element accommodated in respective packages being different from each other. The light emitting device mixes output lights from the light emitting units (10, 20, 30) to output white light of a predetermined chromaticity. In an xy chromaticity diagram, the chromaticity of the output light from each of light emitting units (10, 20, 30) is located at a distance from the predetermined chromaticity. The difference between the chromaticity of the output light from each of the light emitting units (10, 20, 30) and the predetermined chromaticity is not greater than 0.04.

Abstract: A data processing device according to one or more embodiment is disclosed. The data processing device may include a first power-on reset circuit that generates a first power-on reset signal depending on power source voltage, and a processor that activates based on a first power-on reset signal generated by the first power-on reset circuit and that runs software. The processor determines if the normal first power-on reset signal is used to cause the processor to activate and run the software.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A pipeline processing unit includes a fetch unit that fetches the instruction for the thread having an execution right, a decoding unit that decodes the instruction fetched by the fetch unit, and a computation execution unit that executes the instruction decoded by the decoding unit. When the WAIT instruction for the thread having the execution right is executed, an instruction holding unit holds instruction fetch information on a processing target instruction to be processed immediately after the WAIT instruction. An execution target thread selection unit selects a thread to be executed based on a wait command and, in response to a wait state started from the execution of the WAIT instruction being canceled, processes the processing target instruction from decoding thereof based on the instruction fetch information on the processing target instruction held in the instruction holding unit.

Abstract: A light emitting device (1) includes: three or more light emitting units (10, 20, 30) that individually include blue light emitting element, a wavelength range of the blue light emitting element accommodated in respective packages being different from each other. The light emitting device mixes output lights from the light emitting units (10, 20, 30) to output white light of a predetermined chromaticity. In an xy chromaticity diagram, the chromaticity of the output light from each of light emitting units (10, 20, 30) is located at a distance from the predetermined chromaticity. The difference between the chromaticity of the output light from each of the light emitting units (10, 20, 30) and the predetermined chromaticity is not greater than 0.04.

Abstract: An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.

Abstract: A SJ power MOSFET having a super junction structure includes a P? pillar layer buried in a drift layer as an N? pillar layer and including a P pillar upper layer and a P pillar lower layer, wherein the P? pillar layer is configured to fulfill the relationships: Db>Da and Ca>Cb, where Da is a defect density of the P pillar upper layer, Ca is an impurity concentration of the P pillar upper layer, Db is a defect density of the P pillar lower layer, and Cb is an impurity concentration of the P pillar lower layer, so as to achieve a higher switching speed and ensure higher breakdown stability.

Abstract: A semiconductor device, comprising a nitride semiconductor layer, a switching element, and a driving transistor; the switching element comprises: a first portion of a first electrode formed on the nitride semiconductor layer; a second electrode formed on the nitride semiconductor layer; and a first control electrode formed on the nitride semiconductor layer and located between the first portion of the first electrode and the second electrode; the driving transistor comprises: a second portion of the first electrode formed on the nitride semiconductor layer and connecting the first portions of the adjacent first electrodes to each other; a third electrode formed on the nitride semiconductor layer and transmitting a signal to the first control electrode; and a second control electrode formed on the nitride semiconductor layer and located between the second portion of the first electrode and the third electrode.

Abstract: A multicore system according to one or more embodiments is disclosed, which may include processors that execute processing different from each other, a selector that selects one of the processors, a checker processor, a comparator that compares an external state of the processor selected by the selector with an external state of the checker processor, or compares an internal state of the processor selected by the selector with an internal state of the checker processor, and a controller that determines that the selected processor or the checker processor is abnormal in response to the external states or the internal states doing not match each other based on comparison results obtained by the comparator.

Abstract: A semiconductor device includes: a semiconductor base; a trench insulating film which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in a film thickness direction of the semiconductor base and including a charged region which is charged positively; and a gate electrode provided on the trench insulating film within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.

Abstract: Provided is a switching power supply device capable of easily realizing multi-phase operation and current balancing with the number of operation phases depending on the amount of load.

Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.

Abstract: A semiconductor device includes: a semiconductor base 10 in which a first trench 101 is formed in a mesh-like shape in a plan view and a second trench 102 is formed in a mesh opening surrounded by the first trench 101; a first semiconductor element 1 which is formed in the semiconductor base 10 and includes a first gate electrode 81 provided within the first trench 101; and a second semiconductor element 2 which is formed in the semiconductor base 10 and includes a second gate electrode 82 provided within the second trench 102 surrounded by the first gate electrode 81.