Patents Assigned to SGS-Thomson Microelectronics S.A.
  • Electrical programmable non-volatile memory integrated circuit with option configuration register
    Patent number: 6104634
    Abstract: An electrically programmable non-volatile memory integrated circuit includes: read/write resources; a first bit line; a second bit line; an option configuration register consisting of at least one bit; a reading mechanism; and a writing mechanism. The option configuration register includes, for the at least one bit: a bistable element including at least one memory cell, and a static memory element. The at least one memory cell is coupled to the first bit line and to the second bit line, and the static memory element is coupled to the bistable element. The reading mechanism is for reading a state of the static memory element, and it utilizes the first and second bit lines and the read/write resources. The writing mechanism is for setting the state of the static memory element, and it utilizes the first and second bit lines and the read/write resources.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Laurent Rochard
  • Method for improving the intermediate dielectric profile, particularly for non-volatile memories
    Patent number: 6104058
    Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Claudio Brambilla, Giancarlo Ginami, Stefano Daffra, Andrea Ravaglia, Manlio Sergio Cereda
  • Apparatus and method for decompressing high definition pictures
    Patent number: 6104751
    Abstract: A system for processing compressed data corresponding to pictures includes a decoding mechanism, providing a picture memory with decoded picture data. The decoding mechanism requires, for decoding a current block of a previously decoded picture. A plurality of decoders are associated with respective picture memories, each storing a specific slice of corresponding blocks of a plurality of pictures, as well as at least one margin which is liable to be a predictor block serving to decode a block of the specific slice.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Alain Artieri
  • Semiconductor integrated capacitive acceleration sensor and relative fabrication method
    Patent number: 6104073
    Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Paolo Ferrari, Mario Foroni, Benedetto Vigna, Flavio Villa
  • Circuit for the detection of changes of address
    Patent number: 6104644
    Abstract: A memory is provided with an addressing circuit comprising an address bus to convey address signals, biasing and selector switch circuits connected to the address bus for the selecting and biasing of lines of the memory and write circuits for the writing of data in cells of the memory. The memory comprises an enabling circuit to enable an operation of writing in memory. This enabling circuit comprises a circuit to memorize a designated address or to write data elements, a comparison circuit to compare a current address available on the address bus with the designated address and a blocking circuit to prevent the writing when the comparison reveals a difference of address.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Alessandro Brigati
  • Device for organizing the access to a memory bus
    Patent number: 6101564
    Abstract: This invention relates to a device for organizing access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: August 8, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Claude Athenes, Bernard Louis-Gavet
  • Memory cell for EEPROM devices, and corresponding fabricating process
    Patent number: 6097057
    Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: August 1, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Giovanna Dalla Libera, Bruno Vajana, Roberta Bottini, Carlo Cremonesi
  • Digital television signal flow regulation
    Patent number: 6097446
    Abstract: The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: August 1, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Michel Imbert, Serge Volmier, Xavier Cauchy
  • Method for the identification of an integrated circuit and associated device
    Patent number: 6094691
    Abstract: A method is for the identification of an integrated circuit, and includes steps for writing, in a volatile register, a required number; the decoding, in the integrated circuit, of the required number and the reading of the identification number if the integrated circuit is not compatible with the required circuit or the reading of the required number if the integrated circuit is compatible with the required circuit. An identification device may include a non-volatile register, a volatile register, a decoder and a router.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: July 25, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Francine Burgard
  • Dynamic computation of the ratio between two bitstreams representing slowly varying quantities and Dolby Pro Logic decoder
    Patent number: 6094488
    Abstract: The ratio y(n) of two digital values, respectively a(n) and b(n), representing the n.sup.th elements of two respective sequences of digital input data representing two quantities slowly varying in time, is obtained by computingy(n)=y(n-1)+g*[a(n)-b(n)*y(n-1)]wherein g represents a multiplying factor. Within the domain of the z transform, the expression becomes:Y(z)=z.sup.-1 *Y(z)+g[A(z)-B(z)conv Y(z)*z.sup.-1where conv indicates an operation of convolution and which, for input sequences corresponding to signals filtered through a lowpass filter with a time constant greater than or equal to 3 msec is simplified to: ##EQU1## The approximation is exceptionally good and computation thereof may be achieved by the use of relatively simple hardware, without severely burdening the workload of a microprocessor.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: July 25, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Marco Bianchessi, Sandro Dalle Feste, Nadia Serina, Davide Sanguinetti
  • Process for multiplying the frequency of a clock signal with control of the duty ratio, and corresponding device
    Patent number: 6091270
    Abstract: A frequency-doubling block includes an input terminal for the incident signal, a first variable delay cell linked to the input, and an EXCLUSIVE OR gate, one input of which is linked to the output of the first delay cell, the other input of which is linked to the input terminal, and the output of which is able to deliver an output clock signal at twice the frequency of the incident signal. A comparison circuit compares the duty ratio of the output signal with a predetermined reference value and a modulation circuit modulates the value of the first delay as a function of the result of the comparison.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: July 18, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Xavier Cauchy
  • Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material
    Patent number: 6087729
    Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: July 11, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Gianfranco Cerofolini, Giorgio De Santi, Giuseppe Crisenza
  • Voltage regulator with internal generation of a logic signal
    Patent number: 6084389
    Abstract: The present invention relates to a voltage regulator including at least one input terminal for receiving a supply voltage; a circuit for generating a reference voltage proportional to a desired regulated output voltage; an amplifier of a signal of error between the reference voltage and the output voltage assigned with a coefficient of proportionality; a capacitor connected between an output terminal and the ground, further including means for supplying at least the circuit and the amplifier with the output voltage in case of a deficiency or a disappearing of the supply voltage present on the input terminal.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: July 4, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Marc Gens, Fran.cedilla.ois Van Zanten
  • Parallel-access memory and method
    Patent number: 6085280
    Abstract: A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: July 4, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Sebastien Zink
  • MPEG decoder with reduced memory capacity
    Patent number: 6081298
    Abstract: This MPEG Decoder relates to the decoding of an image that can be of a bi-directional type requiring data from two previously decoded images, each image being displayed in two successive fields corresponding to lines with different parities. Each bi-directional image is decoded twice during its display time, a first time as a first field of the image is being directly displayed, and a second time as the second field is being directly displayed.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: June 27, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Alain Artieri
  • Memory cell for EEPROM devices, and corresponding fabricating process
    Patent number: 6080626
    Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: June 27, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Bruno Vajana, Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera
  • Self-protected, low emission electronic device for driving a warning horn
    Patent number: 6081184
    Abstract: A self-protected, low emission electronic device for driving a warning horn includes a coil powered from a battery through a control push-button adapted for operation by a user and included in an electric connection between a terminal of the coil and the battery. The device includes a protective circuit portion connected between the battery and the warning horn. The protective circuit portion includes a bridge structure of power components. At least a pair of the power components are MOS power transistors of which one is driven by a charge pump.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: June 27, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Rosario Scollo
  • Magnetic read/write head that detects open and short-circuits
    Patent number: 6081396
    Abstract: A read/write head for a magnetic medium magnetic is modified by the addition to it of a parallel-connected resistor and by the measurement of the difference in voltage at the terminals of this unit, on the one hand when the read/write head and the resistor are perfectly connected and, on the other hand, when one of the connections is in an open circuit condition or even in short-circuit condition with respect to ground. Consequently, a measurement is taken, preferably, of the state of connection of the read/write head when it is in read mode and not when it is in write mode. It is shown that far greater reliability in the detection of this type of defect is obtained, in avoiding false alarms.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: June 27, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Marc Henri Ryat
  • Gain modulated sense amplifier and method of operating the same
    Patent number: 6078523
    Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: June 20, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Video signal digital slicing circuit
    Patent number: RE36749
    Abstract: An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V.sub.T).
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: June 27, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jacques Meyer