Abstract: To control low-pressure fluorescent lamps, there is provided a device comprising a first change-over switch circuit and a second change-over switch circuit, respectively including a first power transistor and a second power transistor. The first change-over switch circuit first of all measures the period of time when the second power transistor is on. Then, secondly, it turns the first power transistor on for a period equal to the period measured.

Abstract: A generator for generating a plurality of predetermined voltage values for non-volatile memories. The generator includes an input node, a plurality of circuit branches, and an output terminal. The input node has a reference voltage and is connected to at least one of the circuit branches. Each of the circuit branches has at least one active element to selectively and independently turn on and turn off each of the circuit branches by a voltage applied to a control terminal of each active element. The output terminal connects to at least one of the circuit branches and supplies a voltage level based on the reference voltage and a voltage drop across each activated circuit branch. Alternatively, the output terminal supplies a floating voltage level in the event of one or more of the active elements along each of the circuit branches being turned off so as to isolate the input node from the output terminal.

Abstract: A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at "0". A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.

Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: An apparatus and method for reading of a memory associated with a central processing unit that does not permit a fraudulent individual to discover the addressing codes of the memory corresponding to the performance of a particular wherein the successive codes for the addressing of the memory are deduced from one another according to a function of prediction defined by the programmer. These addressing codes are verified by the addressing circuits of the memory by means of a computation and comparison procedure that know the prediction function.

Abstract: The present invention relates to a differential stage including two first transistors respectively controlled by two components of a differential input voltage, these transistors being connected to a common current source and forming two differential output branches. The stage includes an auxiliary transistor controlled by the common mode of the differential input voltage and connected to take from each of the output branches a portion of the current established by the common current source.

Abstract: This invention relates to a circuit for calculating a syndrome on packets of n p-bit data, including a syndrome `register receiving the sum of each received datum and of the contents of the syndrome register modified by a first interconnection matrix corresponding to the p-th power of a generator polynomial. Each received datum defines a new packet of n data and the above-mentioned sum includes the datum preceding the new packet, modified by a second interconnection matrix corresponding to the n-th power of the first matrix.

Abstract: The present invention relates to a system for providing a regulated voltage meant to supply a load, including a source for providing a substantially constant current approximately corresponding to the maximum current likely to be surged by the load, and a device receiving the constant current and regulating the load supply voltage, at least one capacitor being connected between an output terminal of the regulation device and the ground.

Abstract: The present invention relates to a method for correction of the horizontal scanning current of a cathode-ray tube based on a modulation of this scanning current by a substantially parabolic signal at the image frame frequency, obtained by a squaring of a current ramp, including inflecting the ends of this current ramp before its squaring.

Abstract: The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.

Abstract: The present invention relates to a microprocessor including an operator dedicated to a signature calculation over a bit sequence, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word including a group of bits forming a successive portion of the sequence, and the second parameter of which indicates the length of the group of bits, the operator responding to the dedicated instruction by updating a signature register with a signature calculated over the content of the signature register and over the group of bits.

Abstract: The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0<y<30%; and depositing an Si.sub.1-z Ge.sub.z layer of desired thickness, where z>50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

Abstract: A battery-charging electronic device comprises a current generator adapted to supply a charging current to a battery and a controlled current edge switch having a circuit for controlling the switching edges of current being flowed through a power transistor. The switching edge control circuit comprises a controlled edge variable voltage generator for generating a controlled edge voltage signal, a voltage/current converter for converting the voltage signal to a controlled edge current signal, and a driver circuit for the power transistor being input the controlled edge current signal to mirror, onto the power transistor, an output current which is proportional to the controlled edge current signal.

Abstract: The pressure sensor is integrated in an SOI (Silicon-on-Insulator) substrate using the insulating layer as a sacrificial layer, which is partly removed by chemical etching to form the diaphragm. To fabricate the sensor, after forming the piezoresistive elements and the electronic components integrated in the same chip, trenches are formed in the upper wafer of the substrate and extending from the surface to the layer of insulating material; the layer of insulating material is chemically etched through the trenches to form an opening beneath the diaphragm; and a dielectric layer is deposited to outwardly close the trenches and the opening. Thus, the process is greatly simplified, and numerous packaging problems eliminated.

Abstract: A solder ball array package has a mould gate tape that is attached on top of a portion of the top surface of a leadless circuit carrying insulating substrate and on top of a portion of the top metallization pattern. The mould gate tape, which is optionally removable after completion of the moulding process, is such that it does not interfere with the design of the top side metallization pattern.

Abstract: An interconnect track connects, on several metallization levels, an insulated gate of a transistor to a discharge diode within an integrated circuit. The interconnect track comprises a first track element extending under the highest metallization level, having a first end connected to the gate and having a length greater than a predetermined critical length. This first track element includes an interrupted track portion at a site a first distance less than the critical length away from the first end. This point is compatible with the placement of the metallization level above, and extends between two insulating layers on the same metallization level. The two branches of the interrupted portion are mutually connected by a metallic filling contact which also extends in the insulating support layer of the metallization level immediately above that containing the interrupted track portion.

Abstract: An assembly ring includes a collar for removable assembly of the ring on a test head. The assembly ring further includes a disk having an open central portion and meant for supporting a periphery of a wafer, which provides an interface of electrical contact transfer between a test head and a circuit to be tested. A rotatable connection including a ball bearing is provided between the disk and the collar.

Abstract: An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of the first transistor, and a quenching element having a terminal connected to a base terminal of the first transistor. The quenching element is formed within the base region or the emitter region of the first transistor.

Abstract: A control device for a hands-free telephone set automatically controls microphone and amplifier gains so that a feedback loop has less than unity gain to avoid circuit instability and resultant self-oscillation. An emission channel includes a microphone, a signal compressor and a controllable attenuator. A reception channel includes a signal compressor, an adjustable attenuator and a loudspeaker. The combination of the emission and reception channels form an amplification loop whereby the output of the reception channel is acoustically coupled to the input of the emission channel while the output of the emission channel is coupled to the input of the reception channel through a common telephone line. To avoid circuit oscillation, a circuit initially sets the gain of the loop to a predetermined value slightly less than unity (0 db) and subsequently maintains the loop gain constant by maintaining the sum of the compressor and attenuator gains at a fixed value.