Abstract: A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

Abstract: A capacitive array particularly for converters, comprising a plurality of unitary capacitors, the number of the unitary capacitors being equal to 2.sup.n, where n is the number of bits of the binary code required in output, the unitary capacitors being mutually connectable so as to obtain capacitors in which the capacitance ratio between one capacitor and the adjacent parallel-connected capacitor is equal to a factor of two. The invention is that the factor-of-two capacitance ratio of adjacent capacitors is achieved by mutually diagonally connecting in parallel the unitary-capacitance capacitors of the capacitive array in a preset number according to the capacitance value to be obtained.

Abstract: The present invention relates to a BICMOS technology comparator including: a first stage with differential inputs capable of operating with input voltages which are, in the common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor; a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, and a midpoint of their series connection forming an output terminal of the comparator; and circuitry for controlling the differential stages according to the voltages applied on their inputs.

Abstract: A memory card or chip card reader system in which the reader is connected to a microcomputer by a connection link enabling the connection, in a branch, of another computer peripheral such as a printer. This link enables the transmission, to the reader, of at least one operation signal. Such a system makes it possible to provide for a reader that has no microprocessor and therefore has no processing function. Furthermore, the microprocessor can possess only one connector common to the reader and printer. Applications to microcomputer links and card readers.

Abstract: A fluid flow meter is of the type including a heated probe sensor of known electric resistance dipped into or swept by a fluid stream having a predetermined velocity. The sensor is capable of converting each flow velocity value to a voltage value, and is connected to a processor operating using fuzzy logic for producing the flow measurements. The sensor may be an NTC thermistor. The thermistor may be powered from a current generator, and the processor may include a neural network. The sensor may include at least two discrete thermistors, one being a hot thermistor and the other being a cold thermistor.

Abstract: The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.

Abstract: Disclosed is a device for protection of stored data comprising protection means to control a signal to enable the programming of a memory, the programming being permitted when the enabling signal is in a first state and prohibited when the enabling signal is in a second state, the protection means including a supply voltage drop detection device to set the enabling signal in the second state when the supply voltage is below a threshold, said device further comprising a time delay circuit capable of setting the enabling signal in the second state during a given period when a control signal goes into a first state.

Abstract: The disclosure relates to integrated circuits and, more particularly, to a power-on-reset circuit. The proposed circuit produces an inhibition signal when the power is turned on, this signal being interrupted after the supply voltage Vcc has reached a first threshold (VS1) (VS1). Furthermore, the circuit has means to re-trigger the inhibition signal when the supply voltage drops by a certain value, in doing so even if the supply voltage remains above the first threshold. The reliability of the integrated circuit is improved. The disclosed circuit is particularly applicable to the inhibition of the writing circuit of an EEPROM memory.

Abstract: An amplifier output stage comprises an output transistor having a control terminal coupled to a first supply rail through a controllable current source, and a main terminal connected to an output terminal of the output stage; and an auxiliary differential stage operatively connected to compare the voltage on the output terminal to a reference voltage and to pull the control terminal of the output transistor towards a second supply rail when the voltage on the output terminal reaches the reference voltage.

Abstract: A semiconductor integrated, storage circuit device having at least a first enable terminal for enabling the device, and a first number of address terminals for inputting an external address formed of a corresponding first number of bits. The device comprises a plurality of data storage elements which are addressable by an internal address formed of a second number of bits larger than said first number, and further comprises address storage elements which are coupleable with their inputs to the first enable terminal for storing additional address bits. Thus, the internal address is comprised of the external address and the additional address bits.

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.

Abstract: The present invention relates to a method and a programmable divider of a frequency of a clock signal by an integer by means of a counter, which is programmable by means of n binary signals representing the division ratio, and issuing n binary counting signals of increasing ranks and of decreasing respective frequencies, which consist of performing n-1 logic combinations of the counting signals, and selecting an output signal from among the n-1 logic combinations and n-1 counting signals.

Abstract: A device for identifying a determined repetitive sequence of predetermined signals arriving on a modem. The device includes a delay circuit so that all the words of a sequence are simultaneously present; a combination circuit for providing a combined word; a circuit for calculating the modulus of each combined word and for comparing this modulus with a threshold; a circuit for counting clock pulses corresponding to the rate at which words arrive; a circuit for inhibiting the counting circuit when the modulus of the combined word is lower than the threshold; and a circuit for providing an identification signal when a predetermined number of clock signals is counted.

Abstract: A device that can be integrated into an integrated circuit dedicated to a microprocessor, this circuit comprising a direct memory access circuit and a communications cell, the communications cell comprising a state register and a sequencer that contain first information elements, the direct memory access circuit comprising a control register that contains second information elements, wherein said device comprises action means to enable the communications cell to act directly on bits of the control register in order to make certain of the second information elements identical to certain of the first information elements. Also disclosed is a method designed to eliminate possible conflicts between a direct memory access circuit and a communications cell that are due to information elements of the same nature.

Abstract: An output buffer circuit for logic signals produces an output logic signal from an input logic signal. It comprises a storage circuit capable of storing the logic state of the input signal and an output stage to produce the output signal as a function of the logic state stored in the storage circuit. A control circuit comprises a circuit for the comparison of the input and output signals. The control circuit produces an updating command signal whose logic state represents the relationship existing between the logic states of the input and output signals. This updating signal activates the storage, in the storage circuit, of the state of the input signal.

Abstract: A circuit for shifting the voltage level of a digital signal, comprising a first pair of transistors of a first polarity, which are connected to a high-voltage line, and a second pair of transistors of a second polarity, which are connected to a ground line; the first and second pairs of transistors are connected to each other by means of the drain terminals of the respective transistors; an input voltage is applied to the gate terminals of the first pair of transistors. The circuit further includes a secondary circuit for leveling the gate voltages of the transistors of the first and second pairs, which is connected between the first and second pairs of transistors and whereto at least one reference voltage is applied. The circuit also includes an output stage, whose output is a voltage which is shifted in level with respect to the input voltage.

Abstract: In a static RAM, a complete erasure of the memory is achieved by sequentially propagating an erasure control signal from one group of memory cells to a next group of memory cells through delay circuits calibrated to correspond to a maximum time duration of erasure of the previous group of cells.

Abstract: A method for reducing the RAM requirement for temporarily storing a stream of data blocks in a coding/decoding system of information transferable by blocks, includes the steps of: compressing and coding the data by blocks through a tree search vector quantization (TSVQ); storing TSVQ compressed and coded data in the RAM; and decoding and decompressing in a subsequent reading of the data stored in the RAM the coded and compressed data, thereby reconstituting the stream of digital data blocks.

Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.