Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: Electromigration resistance of aluminum alloy conductors in semiconductor devices is found to significantly increase by rapidly annealing the conductors by employing an annealing cycle with a peak temperature of 520.degree.-580.degree. C. and a cycle time of about 5 to 30 seconds such as is developed by high intensity CW lamps.

Abstract: A memory system of the EEPROM type in which a separate writing circuit is provided for each cell of a related byte thereby permitting one cell to be charged while the other can be simultaneously discharged.

Abstract: A multi-stage amplifier (21, 22, 23, or 24) has three or more amplifier stages (A1, A2, and A3) arranged in a capacitatively nested configuration for frequency compensation. The technique consists of nesting two of the stages together with a pole-splitting capacitor (C1) to form a stable device (21 or 22) and then nesting this device and a third of the stages together with another pole-splitting capacitor (C2) to form the amplifier.

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.

Abstract: A bipolar impedance buffer contains an input transistor (Q1) whose emitter is coupled to that of a like-polarity intermediate transistor (QN). Its collector is coupled to the base of a like-polarity output transistor (QO), while its base is coupled to the collector of an opposite-polarity transistor (QP). A resistor (RN) coupled between the base and collector of the intermediate transistor significantly reduces the output settling time.

Abstract: A voltage reference for providing a reference voltage (V.sub.AB) between a pair of terminals (A and B) contains a diode (D) and a bipolar transistor (Q) whose base is coupled to one electrode of the diode. The collector of the transistor is coupled to a node (C) between one of the terminals (A) and the other electrode of the diode. The emitter of the transistor is coupled to the other terminal (B).

Abstract: A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers.

Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Abstract: A signal translator for converting an input voltage (V.sub.I) into an output voltage (V.sub.O) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V.sub.CC) and a normally constant second supply voltage (V.sub.EE). A reference voltage (V.sub.R) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V.sub.F). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Abstract: A bipolar differential amplifying circuit contains a pair of input transistors (3 and 4) for receiving a differential input signal, a pair of differentially-configured first and second transistor circuits (5 and 6) coupled to the input transistors, and a subtracting circuit (11 and 12) for comparing the sum of the currents through first collectors (5C.sub.1 and 6C.sub.1) of the transistor circuits with the current through a second collector (6C.sub.2) of the second transistor circuit to generate an output signal representative of the input signal. A PN diode (13) is coupled to a second collector (5C.sub.2) of the first transistor circuit. The voltages at the collectors are very close, thereby yielding a high common-mode rejection ratio for the input signal.

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: An amplifier circuit for sensing and refreshing stored information, utilized with a voltage supply. The amplifier is of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes. The circuit comprises first and second cross coupled devices each capable of assuming a high and low conduction state. Restore circuitry means is provided connected between the active devices and the voltage supply for selectively connecting the supply solely to the device assuming a low conduction state. In a dynamic random access memory embodiment means is further provided for alternately precharging the nodes to a predetermined state and applying stored information to the nodes to cause the amplifier to assume first and second conditions in response to stored information.

Abstract: A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

Abstract: A layer of a conductive material consisting of aluminum alone or in combination with a small percentage of copper and/or silicon is formed on a semiconductor surface in a two-step deposition process in such a manner as to largely avoid serious continuity defects in the layer.

Abstract: A bipolar voltage translator contains a pair of differentially coupled transistors (Q1 and Q2) for converting an input voltage (V.sub.IN) supplied to one (Q1) of the pair into an output voltage (V.sub.OUT) taken between the other (Q2) and a first resistor (R9). A further transistor (Q4) coupled through a second resistor (R12) to a V.sub.EE supply provides current for the differential pair. A voltage reference circuit (10) containing at least three serially coupled diodes (S5, J3, and J4) with a resistive voltage divider (R13 and R14) across an intermediate one (J3) of the diodes provides the current-source transistor with a reference voltage (V.sub.REF2) that equals V.sub.EE +(1+.alpha.)V.sub.BE where .alpha. is 0.2-3.0. The ratio of the first resistor to the second is desirably .beta./.alpha. where .beta.is the output voltage swing divided by V.sub.BE. If .beta. is 1 and the transistors are NPN devices, the output voltage level is suitable for current tree logic.

Abstract: A film of titanitum-tungsten nitride is used to provide the dual function of a fuse link between a semiconductive device and an interconnect line in a memory array and of a barrier metal between another metal and a semiconductor region.

Abstract: A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken.

Abstract: A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.