Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: In embodiments, an optoelectronic device comprises a substrate formed of magnesium oxide, and a multi-region stack epitaxially deposited upon the substrate. The multi-region stack may comprise a non-polar crystalline material structure along a growth direction, or may comprise a crystal polarity having an oxygen-polar crystal structure or a metal-polar crystal structure along the growth direction. In some cases, at least one region of the multi-region stack is a bulk semiconductor material comprising Mg(x)Zn(1-x)O. In some cases, at least one region of the multi-region stack is a superlattice comprising MgO and Mg(x)Zn(1-x)O.

Abstract: Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of the substrate. The system includes a heater configured to heat the substrate and a positioning mechanism that allows dynamic adjusting of an orthogonal distance, a lateral distance, and a tilt angle of an exit aperture of a material source relative to the substrate. In some embodiments, the dynamic adjusting is based on a desired layer uniformity for a desired layer growth rate. In some embodiments, the orthogonal distance, the lateral distance, or the tilt angle depends on a predetermined material ejection spatial distribution of the material source.

Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Nix1Mgy1Zn1-x1-y1)(Alq1Ga1-q1)2O4 wherein 0?x1?1, 0?y1?1 and 0?q1?1; and a second epitaxial oxide layer comprising (Nix2Mgy2Zn1-x2-y2)(Alq2Ga1-q2)2O4 wherein 0?x2?1, 0?y2?1 and 0?q2?1. In some cases, at least one condition selected from x1?x2, y1?y2, and q1?q2 is satisfied.

Abstract: The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (AlxGa1-x)yOz, wherein 0?x?1, 1?y?3, and 2?z?4, wherein the (AlxGa1-x)yOz comprises a Pna21 space group, and wherein the (AlxGa1-x)Oz comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Abstract: The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a first epitaxial semiconductor layer on the substrate; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The first epitaxial semiconductor layer can comprise a first oxide material, wherein the first oxide material can comprise a first polar material with an orthorhombic, tetragonal or trigonal crystal symmetry, and wherein the first oxide material can comprise a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Abstract: The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

Abstract: Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

Abstract: Methods and systems of heating a substrate in a vacuum deposition process include a resistive heater having a resistive heating element. Radiative heat emitted from the resistive heating element has a wavelength in a mid-infrared band from 5 ?m to 40 ?m that corresponds to a phonon absorption band of the substrate. The substrate comprises a wide bandgap semiconducting material and has an uncoated surface and a deposition surface opposite the uncoated surface. The resistive heater and the substrate are positioned in a vacuum deposition chamber. The uncoated surface of the substrate is spaced apart from and faces the resistive heater. The uncoated surface of the substrate is directly heated by absorbing the radiative heat.

Abstract: The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (AlxGa1-x)yOz, wherein 0?x?1, 1?y?3, and 2?z?4, wherein the (AlxGa1-x)yOz comprises a Pna21 space group, and wherein the (AlxGa1-x)yOz comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Abstract: Methods and systems of heating a substrate in a vacuum deposition process include a resistive heater having a resistive heating element. Radiative heat emitted from the resistive heating element has a wavelength in a mid-infrared band from 5 ?m to 40 ?m that corresponds to a phonon absorption band of the substrate. The substrate comprises a wide bandgap semiconducting material and has an uncoated surface and a deposition surface opposite the uncoated surface. The resistive heater and the substrate are positioned in a vacuum deposition chamber. The uncoated surface of the substrate is spaced apart from and faces the resistive heater. The uncoated surface of the substrate is directly heated by absorbing the radiative heat.

Abstract: In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer, a second sub-layer, and a third sub-layer, wherein the third sub-layer is adjacent to the light emitting layer. The electrical contact can be coupled to the second sub-layer. The first, second and third sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first and third sub-layers. The first, second and third sub-layers, and the light emitting layer can each comprise a superlattice. The second layer can comprise a chirped superlattice.

Abstract: In some embodiments, a semiconductor structure includes: a first region comprising a first epitaxial oxide material; a second region comprising a second epitaxial oxide material; and a chirp layer located between the first and the second regions. The chirp layer can include alternating layers of a plurality of wide bandgap epitaxial oxide material layers (WBG layers) and a plurality of narrow bandgap epitaxial oxide material layers (NBG layers), wherein thicknesses of the NBG layers and the WBG layers change throughout the chirp layer. The WBG layer can comprise (Alx1Ga1?x1)y1Oz1, wherein x1 is from 0 to 1, wherein y1 is from 1 to 3, and wherein z1 is from 2 to 4. The NBG layer can comprise (Alx2Ga1x?2)y2Oz2, wherein x2 is from 0 to 1, wherein y2 is from 1 to 3, and wherein z2 is from 2 to 4, and wherein x1 and x2 are different from one another.

Abstract: A method for manufacturing a light emitting device can include providing a substrate; forming a first active layer with a first electrical polarity; forming a light emitting region configured to emit light with a target wavelength between 200 nm and 300 nm; forming a second active layer with a second electrical polarity; forming a first electrical contact layer, optionally comprising a first optical reflector; removing a portion of the first electrical contact layer, the second active layer, the light emitting region, and the first active layer to form a plurality of mesas; and forming a second electrical contact layer. Each mesa can include a mesa width smaller than 10 times the target wavelength that confines the emitted light from the light emitting region to fewer than 10 transverse modes, or a mesa width smaller than twice a current spreading length of the light emitting device.

Abstract: In some embodiments, a semiconductor structure comprises a semiconductor layer, a metal layer, and a contact layer adjacent to the metal layer, and between the semiconductor layer and the metal layer. The contact layer can comprise one or more piezoelectric materials comprising spontaneous piezoelectric polarization that depends on material composition and/or strain, and a region comprising a gradient in materials composition and/or strain adjacent to the metal layer. In some embodiments, a light emitting diode (LED) device comprises an n-doped short period superlattice (SPSL) layer, an intrinsically doped AlN/GaN SPSL layer adjacent to the n-doped SPSL layer, a metal layer, and an ohmic-chirp layer between the metal layer and the intrinsically doped AlN/GaN SPSL layer.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising Li(Alx1Ga1?x1)O2 wherein 0?x1?1; and a second epitaxial oxide layer comprising (Alx2Ga1?x2)2O3 wherein 0?x2?1.

Abstract: Embodiments disclose LEDs that operate using impact ionization. Devices include a first conductivity type layer having a first conductivity type, a first intrinsic layer, a charge layer, an impact ionization layer, and a contact layer. The charge layer has a net charge of the first conductivity type and has a material comprising a polar oxide or a non-polar oxide. The charge layer forms a barrier for transporting carriers of the first conductivity type until a bias is applied between the first conductivity type layer and the contact layer to flatten the barrier.