Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: Systems and methods are provided that may be implemented to use angle of arrival (AoA) of a signal transmitted between two Bluetooth Low Energy (BLE) wireless devices to initially authenticate a connection between the two BLE devices. In one example, bonding or pairing with a first BLE device may be restricted to only those other BLE devices having an antenna currently positioned to transmit a signal to the first BLE device from an allowed direction and within a predefined permitted range of AoA relative to the first BLE device.

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

Abstract: A system and method for determining whether a cryptographic system is being observed for power consumption analysis in an attempt to decipher secret keys. The system comprises a first external connection to receive an input voltage, an internal voltage regulator with an external capacitor to produce the desired voltage for the cryptographic system. The internal voltage regulator typically includes a switch that passes current from the first external connection to the external capacitor. By monitoring the frequency at which the switch is activated, it is possible to detect that an external voltage is being applied to the external capacitor. This external voltage is typically used to perform SPA or DPA operations. Thus, the cryptographic system may cease performing any encryption or decryption operations if an external voltage is detected.

Abstract: A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal.

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Abstract: A switch sensor for sensing a state of a switch including a programmable memory, pulse generation circuitry, and comparator circuitry. The memory stores a state value indicative of a detected state of the switch. The pulse generation circuitry provides a pulse-train voltage signal to a first end of the switch, in which the pulse-train voltage signal is toggled between an active state for switch state detection and an inactive state for conserving power. A second terminal of the switch is coupled through resistive circuitry to a supply voltage node and may be coupled to an input terminal of the sensor. The comparator circuitry compares a state of the input terminal with the state value when the pulse-train voltage signal is in the active state for providing a state change signal indicative thereof.

Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first signal; a distortion circuit coupled to the modulator to digitally pre-distort the first signal to compensate for a distortion of an amplifier; a distortion characterization circuit coupled to the distortion circuit to determine the distortion of the amplifier and configure the distortion circuit based on the determined distortion; a mixer coupled to the distortion circuit to upconvert the pre-distorted first signal to a pre-distorted radio frequency (RF) signal; and the amplifier coupled to the mixer to amplify the pre-distorted RF signal and output an amplified RF signal.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A system and method for controlling the current to an LED array is disclosed. The system comprises a microcontroller and an external transistor. The microcontroller has access to the relevant voltages in the circuit, including the voltage across the sense resistor, the voltage at the drain of the external transistor and the high voltage input. By monitoring these voltages, the microcontroller may be able to control the gate input to the external transistor so as to control the current in the LED array. Further, the microcontroller includes provisions to allow for dimming of the LED array, if desired. This configuration allows for post-manufacturing changes to the operation of the system without any hardware modifications.

Abstract: A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.

Abstract: A system and method for determining a position or a movable device is disclosed. The present system utilizes a movable device equipped with a locator device that has an antenna array such that it may determine the angle of arrival of a plurality of incoming beacon signals. In certain embodiments, the movable device is also able to measure its distance travelled. By knowing its distance moved and the angle of arrival from each beacon, the locator device is able to calculate its position as well as the position of each beacon. This procedure may be executed at regular intervals so that the movable device accurately determines its position.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: A device, method and software program that allows a network device to remain synchronized to a master device while minimizing its own power consumption is disclosed. The network device exits a low power mode at regular intervals in order to receive a synchronous communication from a master device. Once the network device has received enough information to confirm that this synchronous communication is from the correct master device, the network device may then return to the low power mode, even before the entirety of the synchronous communication has been received. This may reduce the time that the network device is in the active state by more than 90% in certain instances.

Abstract: A wireless device may include: a radio frequency (RF) front end circuit to receive and process an RF signal; a mixer to downconvert the RF signal to a second frequency signal; a digitizer to digitize the second frequency signal; a channel filter to channel filter the digitized signal; a selection circuit having a first input coupled to the channel filter and a plurality of outputs each to couple to one of a plurality of demodulators; and the plurality of demodulators coupled to the selection circuit. The selection circuit may route the channel filtered digitized signal to a first demodulator of the plurality of demodulators based on a first configuration setting. The wireless device may also include a non-volatile storage with a configuration file including the first configuration setting. The configuration file may be automatically generated by a hardware configurator in response to a plurality of user input parameters.

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.