Abstract: A system and method for allowing a companion device to serve as a user interface for another network device is disclosed. The companion device includes a display element, an input device and a software program that enables the companion device to create standard graphical items on that display. The network device transmits a list of graphical descriptors to the companion device, which the companion device uses to create the user interface. Additionally, the network device also transmits to the companion device, the commands that the companion device is to transmit based on user input. In this way, the companion device does not require any knowledge of the operation or functionality of the network device in order to serve as its user interface.

Abstract: Systems and methods are provided that may be implemented to use resource filtering to provide multiple different device personalities and/or multiple different resources from a radio frequency (RF)-enabled wireless device or apparatus to one or more other connecting RF-enabled wireless devices across one or more wireless connections. In one example, each different given resource of a wireless device may be associated with at least one filter which may be used by the device to determine which connection/s the given resource may be provided, and a given resource may only be provided to a given connecting device only if the given resource passes the filter.

Abstract: A system and method of keyword spotting using two neural networks is disclosed. The system is in sleep mode most of the time, and wakes up periodically. Upon waking, a limited duration of audio is examined. This may be performed using an auxiliary neural network. If any audio activity is detected in this duration, the system fully wakes and examines a longer duration of audio for keywords. The keyword spotting is also performed by the main neural network, which may be a convolutional neural network (CNN).

Abstract: A loop type ground radiating antenna having dual resonance is disclosed. The antenna including a feeding path that traverses the ground clearance, creating a first portion and a second portion. One or more first capacitors are disposed along a first conductive path between the ground clearance and the edge of the ground layer, proximate the first portion, while one or more second capacitors are disposed along a second conductive path between the ground clearance and the edge of the ground layer, proximate the second portion. An input capacitor is used to feed the feeding path. The values of the input capacitor and the first capacitors determine a resonant frequency of the first feeding loop, while the values of the input capacitor and the second capacitors determine a resonant frequency of the second feeding loop. By proper selection of the capacitor values, a wide bandwidth may be created.

Abstract: A first three state driver injects a first clock signal into a crystal through an input node during a startup phase of a crystal oscillator and a second three state driver injects a second signal into the crystal through an output node during the startup phase. The first and second signals are anti-phase signals. The crystal oscillator circuit includes a first amplifier that is used during starting up and steady-state operation and includes a second amplifier. The injection through the input and output nodes is disabled after a fixed time. After injection ends, the second amplifier is turned on if voltage on the output node has reached a desired voltage and left off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.

Abstract: Systems and methods are disclosed for side-channel attack mitigation for secure devices including cryptographic circuits using block ciphers that are not based upon feedback. For disclosed embodiments, an integrated circuit includes a cryptographic circuit and a controller. The cryptographic circuit performs cryptographic operations in a block cipher AES mode without feedback. The controller outputs control signals to the cryptographic circuit that cause the cryptographic circuit to perform the cryptographic operations on sequential data blocks with an internally permuted order to mitigate block cipher side-channel attacks. The internally permuted order can be generated using one or more random number generators, one or more pre-configured permutated orders, or other techniques.

Abstract: A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.

Abstract: Systems and methods for detecting and protecting against phase manipulation during AoA or AoD operations are disclosed. For AoA operations, the network device receiving the constant tone extension (CTE) generates an antenna switching pattern, which may be randomly generated. The network device then receives the CTE using a plurality of antenna elements. In one embodiment, the network device compares the phase of portions of the CTE signal received that utilize the same antenna element. If the phase of these portions differs by more than a threshold, the network device detects a malicious attack and acts accordingly. In another embodiment, if the AoA algorithm cannot determine the angle of arrival, the network device detects a malicious attack and acts accordingly. For angle of departure operations, the network device that transmits the CTE signal generates the antenna switching pattern and transmits it to the position engine, which performs the comparisons described above.

Abstract: The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.

Abstract: A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as tag, transmitting a packet having a first frequency. The receiver, also referred to as the locator, receives the first frequency and measures the phase at a specific point in time. At a predetermined time, the transmitter switches to a second frequency. This is performed while maintaining phase continuity. The receiver also switches to the second frequency at nearly the same time. The receiver then measures the phase of the second frequency at a second point in time. Based on these two phase measurements, the distance between the transmitter and the receiver may be calculated.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: An apparatus includes a radio-frequency (RF) circuit, which includes a power amplifier coupled to receive an RF input signal and to provide an RF output signal in response to a modified bias signal. The RF circuit further includes a bias path circuit coupled to modify a bias signal as a function of a characteristic of an input signal to generate the modified bias signal. The bias path circuit provides the modified bias signal to the power amplifier.

Abstract: Embodiments include cryptographic circuits having isolated operation with respect to embedded sensor operations to mitigate side-channel attacks. A cryptographic circuit, a sensor, and an analog-to-digital converter (ADC) circuit are integrated into an integrated circuit along with a cryptographic circuit. A sensed signal is output with the sensor, and the sensed signal is converted to digital data using the ADC circuit. Further, cryptographic data is generated using one or more secret keys and the cryptographic circuit. The generation of the cryptographic data has isolated operation with respect to the operation of the sensor and the ADC circuit. The isolated operation mitigates side-channel attacks. The isolated operation can be achieved using power supply, clock, and/or reset circuits for the cryptographic circuit that are electrically isolated from similar circuits for the sensor and ADC circuit. The isolated operation can also be achieved using time-division multiplex operations.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: In one aspect, an apparatus includes: a front end circuit to process incoming radio frequency (RF) signals into orthogonal frequency division multiplexing (OFDM) samples of a plurality of OFDM symbols; a transform engine coupled to the front end circuit to convert the plurality of OFDM samples into a plurality of frequency domain sub-carriers; a demodulator coupled to the transform engine to demodulate the plurality of frequency domain sub-carriers; a channel estimation circuit coupled to the transform engine to determine a first channel estimate based on a first set of pilot sub-carriers of the plurality of frequency domain sub-carriers and a second channel estimate based on the first set of pilot sub-carriers; and a control circuit coupled to the channel estimation circuit to control a configuration of the demodulator based at least in part on a selected one of the channel estimates.

Abstract: A wireless device may include: a radio frequency (RF) front end circuit to receive and process an RF signal; a mixer to downconvert the RF signal to a second frequency signal; a digitizer to digitize the second frequency signal; a channel filter to channel filter the digitized signal; a selection circuit having a first input coupled to the channel filter and a plurality of outputs each to couple to one of a plurality of demodulators; and the plurality of demodulators coupled to the selection circuit. The selection circuit may route the channel filtered digitized signal to a first demodulator of the plurality of demodulators based on a first configuration setting. The wireless device may also include a non-volatile storage with a configuration file including the first configuration setting. The configuration file may be automatically generated by a hardware configurator in response to a plurality of user input parameters.

Abstract: In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the divider circuit, the gating circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.

Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.