Abstract: In one embodiment, an apparatus includes a baseband circuit to generate a plurality of subcarriers of a complex sample of a message to be transmitted, and a compensation circuit coupled to the baseband circuit, the compensation circuit to compensate for IQ mismatch. The compensation circuit may include: a calibration circuit to determine, using a tone signal, gain correction values and phase correction values for a subset of the plurality of subcarriers; and a correction circuit to apply the gain correction values and the phase correction values to the plurality of subcarriers to compensate for the IQ mismatch.

Abstract: The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.

Abstract: In one embodiment, an apparatus comprises: a baseband processor having a preamble generation circuit to generate a preamble for an orthogonal frequency division multiplexing (OFDM) transmission, the preamble generation circuit to generate the preamble having a first portion comprising a first plurality of symbols and a second portion comprising a second plurality of symbols, where the preamble generation circuit is to generate at least some of the second plurality of symbols having at least one frequency disruption between successive symbols of the second portion; a digital-to-analog converter (DAC) coupled to the baseband processor to convert the first plurality of symbols and the second plurality of symbols to analog signals; a mixer coupled to the DAC to upconvert the analog signals to radio frequency (RF) signals; and a power amplifier coupled to the mixer to amplify the RF signals.

Abstract: A mixer in a receiver converts a sounding sequence of alternating ones and zeros to an intermediate frequency signal. A digital mixer converts the intermediate frequency signal to a baseband signal that contains a positive tone and a negative tone. A frequency offset correction circuit generates frequency offset corrections based on frequency offset estimates of the frequency offset between a transmitter of the sounding sequence and the receiver. A frequency adjustment circuit adjusts a frequency of the mixer or the digital mixer to thereby center the positive tone and the negative tone around DC. DFT circuits perform single bin DFTs respectively centered on the positive and negative tones. Phases of the positive and negative tones are calculated based on outputs of the DFT circuits and the phases are used to determine fractional time value associated with a distance measurement between the transmitter and receiver.

Abstract: A device and method for improving the accuracy of angle of arrival and departure computations is disclosed. The device and method rely on manipulation of the antenna switching pattern to achieve an improved calculation of arrival angle. In one embodiment, the device calculates an estimate angle of arrival using conventional methods. The device then determines which of a plurality of different antenna switching pattern yields the more accurate results at this estimated angle of arrival. The AoA measurement is then repeated using the preferred antenna switching pattern. In another embodiment, the device captures the amplitude and/or phase of the signal from each antenna element. The device then sorts these antenna elements and defines a preferred antenna switching pattern based on the sort list. The AoA measurement is then performed using the preferred antenna switching pattern. In another embodiment, neural networks may be utilized to determine the preferred antenna switching pattern.

Abstract: A plurality of physically unclonable function (PUF) bit cells are surveyed by supplying a plurality of threshold control values to the PUF bit cells. Survey results associated with each of the threshold control values are evaluated to determine a threshold control pair having a positive threshold control value and a negative threshold control value among the plurality of threshold control values that results in a desired number PUF bit cells that are strong ones and that are strong zeros.

Abstract: Systems and methods for improving encrypted transmissions between nodes in a network are disclosed. In one embodiment, two sets of nonce values are used to monitor communications between each pair of network devices, wherein one set of nonce values is used for packets transmitted from a first node to a second node, and the second set of nonce values is used for packets transmitted from the second node to the first node. These nonce values are used to encrypt packets transmitted between the two nodes. In this way, the probability of loss of synchronization may be reduced, especially in configurations where there is an intermediate node between the first node and the second node. In another embodiment, the possibility of a delay attack is minimized by the intentional resetting of security parameters.

Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

Abstract: A test system for high voltage testing of semiconductor devices including at least one test socket and a docking plate assembly. Each test socket includes a socket enclosure for encompassing first and second contact finger assemblies, in which the socket enclosure may include a cover and alignment plate. At least one test socket is embedded within the docking plate assembly which is configured to mount between high voltage test head and a pick and place handler. The docking plate assembly and each test socket includes one or more site openings each for receiving a corresponding device under test (DUT) during a high voltage test procedure. Each contact finger assembly includes at least one contact finger configured as an elongated conductor with a bent tip for electrically interfacing a pad of the DUT.

Abstract: A system and method for determining a position or a movable device is disclosed. The present system utilizes a movable device equipped with a locator device that has an antenna array such that it may determine the angle of arrival of a plurality of incoming beacon signals. In certain embodiments, the movable device is also able to measure its distance travelled. By knowing its distance moved and the angle of arrival from each beacon, the locator device is able to calculate its position as well as the position of each beacon. This procedure may be executed at regular intervals so that the movable device accurately determines its position.

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

Abstract: Systems and methods for detecting and protecting against phase manipulation during AoA or AoD operations are disclosed. For AoA operations, the network device receiving the constant tone extension (CTE) generates an antenna switching pattern, which may be randomly generated. The network device then receives the CTE using a plurality of antenna elements. In one embodiment, the network device compares the phase of portions of the CTE signal received that utilize the same antenna element. If the phase of these portions differs by more than a threshold, the network device detects a malicious attack and acts accordingly. In another embodiment, if the AoA algorithm cannot determine the angle of arrival, the network device detects a malicious attack and acts accordingly. For angle of departure operations, the network device that transmits the CTE signal generates the antenna switching pattern and transmits it to the position engine, which performs the comparisons described above.

Abstract: A method for communicating between a first radio frequency communications device including a first local oscillator and a second radio frequency communications device including a second local oscillator includes receiving a packet using a receiver of the first radio frequency communications device. The method includes detecting an average frequency offset based on sequential samples of the packet. The method includes applying a first adjustment to the first local oscillator to reduce a frequency offset between the first local oscillator and the second local oscillator. The first adjustment is based on the average frequency offset. The method includes, after adjusting the first local oscillator, transmitting a second packet to the second radio frequency communications device by the first radio frequency communications device using the first adjustment and the first local oscillator.

Abstract: A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

Abstract: A system and method of determining the angle of arrival or departure using a neural network is disclosed. The system collects a plurality of I and Q samples as a packet containing a constant tone extension is being received. The I and Q samples are used to form I and Q arrays, which are used as the input to the neural network. The neural network produces a first output representative of the azimuth angle and a second output representative of the elevation angle. In certain embodiments, the neural network is capable of detecting a plurality of angles, where, for each angle, there are three outputs, a first output representative of the azimuth angle, a second output representative of the elevation angle and a third output representative of the relative amplitude. In some embodiments, the neural network is configured to determine the carrier frequency offset of an incoming signal as well.

Abstract: A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.

Abstract: In an embodiment, an apparatus includes: a sensor to sense real world information; a digitizer coupled to the sensor to digitize the real world information into digitized information; a signal processor coupled to the digitizer to process the digitized information into an image; a discriminator coupled to the signal processor to determine, based at least in part on the image, whether the real world information comprises an anomaly, where the discriminator is trained via a generative adversarial network; and a controller coupled to the discriminator.

Abstract: In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.

Abstract: A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.