Abstract: A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.

Abstract: In embodiments of the present disclosure improved capabilities are described for an RF wireless energy-harvesting device comprising an energy-harvesting mechanism, a message generation facility, and a transmission facility, wherein the RF wireless energy-harvesting device generates electrical energy through the energy harvesting mechanism from a harvesting action, generates a message through the message generation facility, and transmits the message through the transmission facility to a second wireless device, wherein the second wireless device is a second RF wireless energy-harvesting device, a networked device, a mesh network node, or the like.

Abstract: Systems and methods for controlling devices, including controller and actuators are disclosed. Actuators may be devices where remote control of the device or devices is convenient, such as lights, window shades, fans and similar items. In one method, controllers are adapted to send commands from a first controller to an actuator and to a second controller, and from the second controller to the actuator and to the first controller, where the controllers store a state of the actuator as a result of the actuator executing the command.

Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

Abstract: A method includes generating first frequency metrics for a first received network clock signal using a local reference clock signal. The method includes, in response to the first received network clock signal being available and satisfying a quality metric, generating a network delay estimate using a first error estimate based on the first received network clock signal, and updating stored frequency metrics for the first received network clock signal with the first frequency metrics. The method includes generating an output clock signal based on received packets and the network delay estimate. The first frequency metrics for the first received network clock signal may include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

Abstract: An apparatus for providing a clock signal based on a received clock signal includes a time-to-digital converter configured to generate timestamp information based on the received clock signal. The apparatus includes a first filter configured to generate clock period information based on the timestamp information. The apparatus includes a phase monitor circuit. The phase monitor circuit includes a second filter configured to provide a mean period signal of the received clock signal based on the clock period information. The phase monitor includes a phase error detection circuit configured to generate a phase error indicator based on a threshold difference value and a difference between the clock period information and expected clock period information. The expected clock period information is based on the mean period signal.

Abstract: An oscillation circuit including a crystal interface, a crystal amplifier, a level detector, a timing circuit, and a controller. When activated, the crystal amplifier drives a crystal coupled to the crystal interface to establish oscillation, and the level detector indicates when a target amplitude is detected. The controller activates the crystal amplifier and uses the timing circuit and the level detector to measure a startup time of oscillation. The measured startup time is used in calculating a wake up time from a sleep mode in time to perform an operation at a scheduled time. The startup time may be adjusted or averaged and may be remeasured with temperature change. A method of minimizing startup time of a crystal oscillator includes measuring startup time for determining a delay value for programming a wakeup circuit. Robust startup settings may be used in the event of startup failure due to a sleepy crystal.

Abstract: An apparatus includes a first electromagnetic sensor configured to generate a first sensed signal based at least in part on detection of a first signal having a first wavelength. The apparatus includes a second electromagnetic sensor configured to generate a second sensed signal based at least in part on detection of a second signal having a second wavelength different from the first wavelength. The apparatus includes a processing circuit configured to generate a plethysmogram based at least in part on the first sensed signal and the second sensed signal. The apparatus may include a first emitter configured to emit an optical signal having the first wavelength. The apparatus may include a second emitter configured to emit a reference signal. The first wavelength may be a human-blood-sensitive and human-skin-penetrable wavelength and the second wavelength may be at least one of a human-blood-insensitive wavelength and a human-skin-impenetrable wavelength.

Abstract: A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.

Abstract: Proximity sensing antenna systems include two metallic antenna arms. One antenna arm is connected to an RF transmitter at a radio frequency (RF) feed port, and the other antenna arm is connected to an RF detector (e.g., RF measurement receiver or RF power detector) at an RF sense port. The metallic antenna arms are symmetrically positioned with respect to each other across one or more symmetry axes. The metallic antenna arms can be implemented as inverted-L antennas, dipole antennas, inverted-F antennas, and/or as other antenna arm configurations. Further, the antenna arms can be dimensionally identical and positioned symmetrically about one or more symmetry axes. The antenna system can be used within proximity sensing devices for a wide variety of applications including low power sensing and can also be used for wireless data communication.

Abstract: A wireless receiver including multiple amplifiers coupled in series for amplifying a signal being received, at least one detector that provides a strength indication of the signal being received, multiple AGC schedules each determining a gain reduction schedule for the amplifiers, an AGC schedule selector that selects one of the AGC schedules based on a schedule select input, and an AGC controller that adjusts a gain of at least one of the amplifiers according to a selected AGC schedule based on the strength indication of the signal being received. The AGC schedules may include a first AGC schedule configured for improved SNR performance and a second AGC schedule configured for improved distortion performance. The second AGC schedule may be selected for improved distortion performance when a strong distorting blocker signal is present, and otherwise the first AGC schedule may be selected for better SNR performance.

Abstract: A switch controls current to be supplied to an inductive load when turned on. A clamp circuit clamps a flyback voltage resulting from turning off the switch. The clamp circuit has a first clamping voltage responsive to the switch being turned off, and has a second clamping voltage, higher than the first clamping voltage, responsive to a current level through the inductive load being lower than a predetermined current level. That ensures that as the current comes down to levels required to break contact, the clamp voltage is increased to speed the collapse of the magnetic field when needed to minimize contact wear by maintaining armature momentum.

Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

Abstract: A crystal driver circuit for driving a crystal to oscillate at a resonant frequency including an amplifier having an input coupled to an amplifier input node and having an output coupled to an amplifier output node, a current source that provides a core bias current to the amplifier, a first tune capacitor coupled between the amplifier output node and a reference node, and a second tune capacitor coupled between the amplifier input node and the reference node. The first tune capacitor has a first capacitance that is greater than a second capacitance of the second tune capacitor by a capacitance offset that reduces frequency shift during operation. The first and second capacitances have a combined capacitance that achieves an oscillating signal having a target frequency.

Abstract: A non-volatile memory (NVM) driver includes a function library with native function calls and a hardware abstraction layer for receiving at least one instruction from the function library and providing signals to cause an NVM to execute the at least one instruction. The NVM includes a plurality of sectors, and the NVM driver uses a first portion as an application visible memory, and a second portion for another purpose. The NVM driver maintains the NVM as a circular buffer within the application visible memory. When a native function call is a resizing command, the function library adjusts the circular buffer selectively according to whether the resizing command increases or decreases the application visible memory. When a native function call is a write counter command, the NVM driver selectively creates a new counter object including a counter base and a plurality of increment locations using a next location pointer.

Abstract: In one embodiment, an apparatus includes a voltage controlled oscillator (VCO) to output an oscillating signal. The VCO may have a tank formed of at least one capacitor coupled in parallel with at least one inductor, and a plurality of transconductors to provide energy to the tank. At least one of the plurality of transconductors can be controllably switched to be coupled to the tank or to be decoupled from the tank.

Abstract: A test system for testing semiconductor chips including a docking plate, a test card, chip sockets, a stiffener, and test electronics. Each test card has a uniform card configuration that may be used with any of several different handlers. Each test card includes conductive pads electrically coupled to and longitudinally offset from a socket interface along a length of the test card. The stiffener includes a test interface including conductive pins for electrically interfacing the conductive pads of the test card. The test card is supported by the stiffener so that it remains undeformed as each chip is plunged into a test socket. The test interface includes a basin that is covered by the test card to form a thermal isolation cavity for thermal separation from the test electronics. A uniform radio frequency interface is provided between each test card and a corresponding test interface.

Abstract: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.