Abstract: A system and method for minimizing the likelihood that the secret key used by a bootloader is compromised is disclosed. A bootloader is installed on the device. The bootloader is a software program that performs many functions. These functions may include checking the checksum of the incoming software image for integrity, decrypting the incoming software image using a secret key, deleting data in the FLASH memory, installing the new software image in the FLASH memory and other functions. The bootloader utilizes various techniques to track the versions of the software image being installed. The method counts the number of incomplete attempts that are made when trying to update the software image. By monitoring these parameters, the bootloader can determine when a malicious actor is attempting a side channel attack. In response, the bootloader may not allow a new software image to be loaded or the secret key to be accessed.

Abstract: An apparatus includes a digital frequency synthesizer (DFS). The DFS includes a time-to-digital converter (TDC) to provide an output signal that represents a phase difference between a reference signal and a feedback signal. The DFS further includes a scaling circuit, which has an adaptively changed gain, to provide a scaled residue signal used to cancel an effect of the residue signal in the DFS.

Abstract: A system and method of performing temperature compensation based on temperature of a crystal. An integrated circuit includes a clock circuit, a memory, an interface developing a sense voltage indicative of a temperature of the crystal, and a controller. The memory stores compensation values including nominal values based on a nominal third order polynomial that defines a nominal frequency versus temperature relationship of a crystal design representing multiple crystals, and a pair of adjustment values derived from two temperature-frequency error points. The controller determines a temperature value based on the sense voltage, calculates a frequency offset using the temperature value and the compensation values to solve a compensated third order polynomial defining a compensated frequency versus temperature relationship of the crystal, and adjusts a clock signal of the clock circuit using the frequency offset. A Wi-Fi device may be optimized for industrial IoT operating within an extended temperature range.

Abstract: A wireless receiver powers up shortly before the expected arrival of a beacon frame, and upon detection of a beacon frame from an access point the station is associated with and determination of subsequent fields of interest, including at least a TIM field, the receiver powers down. At the previously identified fields of interest, the receiver powers up and uses previously stored values to continue packet demodulation, thereafter examining the TIM field to determine whether the AP has packets to transmit to the station.

Abstract: A technique for operating a driver includes enabling the driver to provide a first current through a first terminal of a driver device of the driver in a first mode of operation. The method includes sensing a voltage drop across the first terminal and a second terminal of the driver device to generate a sensed voltage level indicative of the voltage drop. The method includes generating a comparison output signal indicative of a comparison of the sensed voltage level to a threshold voltage level. The method includes selectively enabling the driver to provide a second current in a second mode of operation based on the comparison output signal. The first current may be less than the second current. The enabling may include enabling a first portion of the driver device using a first control signal, while a second portion of the driver device is disabled using a second control signal.

Abstract: A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.

Abstract: A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

Abstract: A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A wireless receiver including a gain network that adjusts a gain of a received wireless signal and provides an RF signal, a level detector that provides a level indication while a strength of the RF signal is at least an RF level threshold, a timing system that provides a timing value indicative of a total amount of time that the level indication is provided during a timing window, a gain up disable circuit that provides a gain up disable signal when the timing value reaches a low threshold, a blocker strength detect circuit that provides a gain down request signal when the timing value reaches a high threshold, and an AGC circuit that does not increase the gain of the gain network while the gain up disable signal is provided, and that allows a reduction of the gain of the gain network while the gain down request signal is provided.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: A system and method for determining whether a gateway device, having two different network interfaces, is able to successfully operate as a Pseudo-Bridge. The gateway device transmits a message to a known network service entity on each of its network interfaces. For example, the gateway device may transmit a DHCP request on both its network interfaces. Alternatively, the gateway device transmits a message to an application server. If the network service entity on each network responds with the same IP address, a network loop is assumed to exist. In this case, the gateway may operate as a traditional router. If the network service entities on the two networks respond with different IP addresses, the gateway device operates as a Pseudo-Bridge. In this way, the network operates correctly in all scenarios.

Abstract: The present invention relates to a method and system of secure wakeup in a communication system. The method comprises: transmitting a predetermined wakeup code by a wakeup transmitter of a first node to a wakeup receiver of a second node using a first communication link; establishing a protocol for future wakeup codes periodically between the first node and the second node using a second communication link; wherein the wakeup code is updated based on at least one of: the protocol for future wakeup codes, a first function of time defined by protocol for future wakeup codes, a second function of number of wakeups defined by protocol for future wakeup codes; comparing the wakeup code received by the second node with the wakeup code sent by the first node; and if the wakeup code received by the second node matches a template wakeup code derived from a protocol for future wakeup codes, then the receiver wakes up; otherwise the receiver does not wakeup.

Abstract: A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

Abstract: A system and method for transmitting packets to a plurality of network devices that cannot be accessed via a single hop. The system includes a source, which issues a multicast message to those network devices in close proximity, and also transmits an encapsulated multicast message to a distribution node. This encapsulated multicast message may be routed using traditional routing protocols. The distribution node then transmits the multicast message to those network devices within close proximity. The distribution node may also have the ability to transmit singlecast messages to those network devices, if necessary, to perform retries.

Abstract: A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

Abstract: A charge pump system including charge pump circuitry, a charge pump controller, and current limit circuitry. The charge pump circuitry has an input coupled to a supply input node and has an output for developing a drive voltage. The charge pump controller controls the charge pump circuitry to increase the drive voltage above a supply voltage provided to the supply input node. The current limit circuitry limits current through the charge pump circuitry to a limited current level that is less than a maximum current level during a current limit mode to reduce current spikes at the nodes of the charge pump system that may generate EMI. A current mirror may be used as the current limit circuitry to directly limit current through switches of the charge pump circuitry. The timing of the charge pump switches may also be modified such as inserting strategic delays to reduce the current spikes.

Abstract: A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.

Abstract: A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.