Abstract: In one aspect, a method includes: receiving, in a configurator for a wireless receiver, a plurality of user-defined parameters for configuring the wireless receiver for wireless communication, the user-defined parameters including pulse shaping information of a pulse shaper of a wireless transmitter to be in communication with the wireless receiver and channel filter information of a channel filter of the wireless receiver; generating a plurality of frequency signals based on a corresponding plurality of predetermined bit sequences and at least two of the plurality of user-defined parameters including the pulse shaping information and the channel filter information; setting a first nominal symbol value based at least in part on an oversampling rate for a demodulator of the wireless receiver; and configuring the wireless receiver with the first nominal symbol value to cause the demodulator of the wireless receiver to operate using the first nominal symbol value.

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Abstract: A wireless receiver has a preamble detection apparatus and method which waits until the expected arrival of a beacon frame, after which power is cyclically applied during a preamble detection interval and a sleep interval until a preamble is detected. The preamble detector has a first mode with a longer preamble detection interval and a second mode with a shorter preamble detection interval. During the preamble detection interval, power is applied to receiver components, and during the sleep interval, power is not applied. The duration of the preamble detection interval is equal to a preamble sensing interval, and if a preamble is detected, power remains applied to a preamble processor for a preamble processing interval. The duration of the sleep interval is the duration of a long preamble less the sum of two times the preamble detection interval plus the preamble processing interval. Phase lock loop (PLL) power is applied a PLL settling time prior to and during the preamble detection interval.

Abstract: A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.

Abstract: A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.

Abstract: An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

Abstract: A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: Systems and methods are provided that may be implemented to create a wireless communication path by opening relatively low power wireless non-broadcast node-to-node connections between network nodes between selected wireless nodes of a mesh network, or by implementing inter-node broadcast routing paths within such a network by selectively broadcasting from selected network nodes, based on one or more inter-node signal transmission characteristics measured between different pairs of nodes of the mesh network. When used, the opened connections may employ non-continuous connection listening intervals that are shorter than observer listening times to communicate over designated data channels in a targeted manner between selected routing nodes in a mesh network.

Abstract: A system and method for gathering and displaying various types of information for a plurality of network devices is disclosed. A system monitoring device is in communication with a plurality of network devices. Each of these network devices transmits information related to power consumption, network activity and/or program execution to the system monitoring device. The system monitoring device stores all of this information and presents it to the user in a manner that allows for investigation of anomalies, power surges and other issues. The system monitoring device may connect to each of the network devices using a wired connection, such as Ethernet or USB.

Abstract: A system for automatically detecting the PHY mode based on the incoming preamble is disclosed. The system includes a multimode demodulator, which includes a preamble detector and a demodulator. The preamble detector is used to determine when the preamble has been received and the PHY mode being used by the sending node. An indication of the PHY mode is supplied to the demodulator, which then decides the incoming bit stream in accordance with the detected PHY mode. In some embodiments, one demodulator, capable of decoding the bit stream in accordance with a plurality of PHY modes is employed. In other embodiments, the system includes a plurality of demodulators, where each is dedicated to one PHY mode.

Abstract: A technique for thermal management of a circuit includes generating a power consumption estimate for the circuit based on a predetermined update amount and a comparison of a sensed voltage level to a predetermined voltage level. The method includes generating a fault signal based on the power consumption estimate and a predetermined power consumption limit. Generating the power consumption estimate may include sensing a voltage drop across a first terminal of a device of the circuit and a second terminal of the device to generate the sensed voltage level. The sensed voltage level may be indicative of the voltage drop. The method may include updating the power consumption estimate by the predetermined update amount in response to a clock signal. The power consumption estimate may be used as a proxy for a measurement of a thermal state of the circuit.

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Abstract: A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc?2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.

Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.

Abstract: A system and method for determining whether a cryptographic system is being observed for power consumption analysis in an attempt to decipher secret keys. The system comprises a first external connection to receive an input voltage, an internal voltage regulator with an external capacitor to produce the desired voltage for the cryptographic system. The internal voltage regulator typically includes a switch that passes current from the first external connection to the external capacitor. By monitoring the frequency at which the switch is activated, it is possible to detect that an external voltage is being applied to the external capacitor. This external voltage is typically used to perform SPA or DPA operations. Thus, the cryptographic system may cease performing any encryption or decryption operations if an external voltage is detected.

Abstract: A system and method of adaptively tuning an antenna of a wireless device including detecting a reflected electrical signal from the antenna during transmission of a wireless signal, converting the reflected electrical signal into at least one parameter indicative of its strength, and adjusting, based on the at least one parameter, a tune value to adjust a matching network during the transmission of the wireless signal to reduce the strength of the reflected electrical signal. The reflected electrical signal may be converted to a corresponding power value, and the tune value may be repeatedly adjusted by an incremental amount or according to a binary search method or the like to reduce the power level of the reflected electrical signal. The reflected electrical signal may be demodulated into demodulated information used to determine an optimal transfer function of the matching network and the tune value may be adjusted accordingly.

Abstract: A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

Abstract: A system and method of allowing a network device to receive a customized version of a reference design is disclosed. In one embodiment, many values that may be subject to customization are no longer fixed by the reference design. Rather, the reference design utilizes rewritable non-volatile memory to store a set of customization values that can be changed, based on a customer's preference. The system also includes a configuration tool, which interfaces with the network device. Using vendor-unique commands, the configuration tool is able to initialize this set of customization values to the values requested by the customer. In operation, the reference design is downloaded into the network device. The configuration tool is then used to establish the customized parameters for a particular customer. This process allows the manufacturer to create one reference design, which can be customized without the need to modify the code or recompile the source code.

Abstract: A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.