Abstract: A transmitter generates programmable upstream and downstream signal pulses for transmission through a fluid whose flow rate is being measured. A receiver receives the upstream and downstream signal pulses and stores digital representations of the pulses. A multiple pass algorithm such as a time domain windowing function and/or an algorithm that equalizes amplitude operates on the stored digital representations prior to demodulation. A quadrature demodulator generates in-phase and quadrature components of the digital representations and an arctangent function using the in-phase and quadrature components determines angles associated with the upstream and downstream signal pulses. The difference between the upstream and downstream angles, from which a difference in time of flight between the upstream and downstream signal pulses can be derived, is used to determine flow rate.

Abstract: A method for operating a communications system includes transmitting a preamble sequence including a plurality of tones. Each tone of the plurality of tones has a first characteristic and a second characteristic. The first characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the first characteristic of each of the other tones of the plurality of tones and the second characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the second characteristic of each of the other tones of the plurality of tones. The first and second characteristics may include relative power and relative phase.

Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.

Abstract: A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

Abstract: A level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.

Abstract: An Internet of Things (IoT) device has a public device identifier and a private device identifier, where the public device identifier is publicly available and the private device identifier is secret but kept in a secure device database as a tuple. A registration request containing encrypted credentials comprising at least a private identifier and optionally a public identifier is sent from the IoT device to an association server in communication with a device database having an association between IoT public identifier and a corresponding IoT private identifier. The association server which receives the registration request and encrypted credentials responds with a registration acknowledgement when the decrypted credentials match the tuple in the device database, or forwards the request to a registration server when it does not. The requesting IoT device receives an acknowledgement and is thereafter able to join the wireless network.

Abstract: A modular integrated circuit test fixture integrates the integrated circuit (IC) handler to IC test fixture alignment interface (the alignment plate) into a daughter card subassembly, which reduces the overall rejection rate of devices due to alignment errors. The test fixture has a plurality of daughter card subassemblies for receiving integrated circuits for testing. Each daughter card subassembly is independently removable from the test fixture and includes a daughter card for a particular size and type of integrated circuit, a plurality of sockets electrically and mechanically coupled to the daughter card to receive respective integrated circuits for testing, and an alignment plate to provide alignment between an IC handler and respective ones of the daughter card subassemblies and to provide alignment for one or more manual test lids. The manual test lids are removed for automatic testing using an IC handler.

Abstract: A system and method for detecting and compensating for carrier frequency offset is disclosed. This system compensates for CFO and calculates a corrected phase. This corrected phase may be used by, for example, an AoX algorithm, such as MUSIC, to more accurately determine the angle of arrival or angle of departure of a signal. In certain embodiments, the system oversamples the incoming signal to create a plurality of samples. The system then determines the phase of each of the plurality of samples and calculates the carrier frequency based on the time derivative of the phase. In certain embodiments, a particular portion of an incoming packet is used to determine the carrier frequency offset. In other embodiments, the system calculates the carrier frequency offset throughout an entirety of the incoming packet. Once the carrier frequency offset is determined, it can be used to adjust the received signals. These adjusted signals are then used to determine the angle of arrival or angle of departure.

Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.

Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.

Abstract: A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.

Abstract: A system for transmission of incident information includes maintaining a table of RSSI values for a plurality of stations. When an incident is detected, the system first sends a broadcast packet with incident information, and next sends a unicast packet to any station below a particular RSSI threshold until the unicast packet is acknowledged or a retransmission interval passes.

Abstract: A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.

Abstract: A system and method of intelligently scheduling actions from multiple network software stacks is disclosed. The scheduler uses information, such as requested start time, slip time, action duration and priority to schedule actions among a plurality of network stacks. In some embodiments, the scheduler attempts to maximize the radio usage by prioritizing the actions based not only on their given priority, but also based on their duration, and the ability for other actions to tolerate a delay in being performed.

Abstract: A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or ?1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

Abstract: A system and method for improving network resiliency is disclosed. The system includes a network having a plurality of network devices and at least one controller. The controller is configured to create various scenes based on the inputs received from the network devices. The controller is also configured to provide alternate instructions to the network devices in the event that the controller is non-functional. The network devices utilize these alternate instructions when attempts to connect the controller are unsuccessful. In this way, the network is able to operate in a limited way even in the absence of the controller.

Abstract: Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.

Abstract: A system and method for determining an optimal configuration of the preamble for use in a wireless network is disclosed. The system and method use the calculated or given channel bit error rate to determine this configuration. There are two important parameters associated with the preamble; its length and the detection threshold. The detection threshold is a measure of how many bits can be incorrect while still detecting the preamble. The optimal value of the detection threshold sets a trade off between false positives and false negatives. In some embodiments, the system uses the channel bit error rate to determine these parameters. In certain embodiments, the detection threshold can be implemented by the receiver without knowledge of the transmitter. By optimizing the configuration of the preamble, the reliability of communications is minimally impacted while power consumption of the network devices is reduced.

Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller parses incoming packets as they are received and generates a request signal once it is determined that the incoming packet is destined for this device. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.