Abstract: An integrated circuit includes an input terminal configured to receive an input signal, a reference voltage node configured to provide a control voltage, and a pass transistor comprising a first terminal coupled to a first node, a control terminal coupled to the reference voltage node, and a second terminal coupled to the input terminal. The control voltage has a control voltage level sufficient to allow a signal to pass from the second terminal to the first terminal. The pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of the input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signal to the first node in response to the voltage level being above the first voltage level. At most, a negligible DC current flows through the input terminal into the second terminal.

Abstract: A system and method for allowing legacy devices to be discovered on a DotDot network is disclosed. The system includes a gateway device to interface between DotDot devices and legacy devices. In some embodiments, the gateway device has a plurality of network interfaces to communicate with these legacy devices. The gateway device discovers the legacy devices that it can communicate with. The gateway device then presents information about these legacy devices in a Resource Directory. In some embodiments, the Resource Directory is maintained within the gateway device. In other embodiments, the gateway device utilizes a Resource Directory that exists on the DotDot network.

Abstract: A crystal driver integrated circuit with external oscillation signal amplitude control including an amplifier core, an input pin and an output pin, an adjustable capacitor, and a controller. The controller operates the amplifier core in any one of multiple operating modes including an oscillator mode and a bypass mode. During the bypass mode, the controller disables the amplifier core and adjusts the adjustable capacitor so that an amplitude of an oscillation signal received via the input pin from an external oscillator has a target amplitude. The external oscillation signal may be capacitively coupled for capacitive voltage division or directly coupled for impedance attenuation. An available voltage may be provided as a source voltage to the external oscillator via the output pin. An internal voltage regulator and/or switch may be included to re-provision the output pin to provide the source voltage during the bypass mode.

Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

Abstract: A divider includes ? divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ? divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.

Abstract: A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.

Abstract: In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

Abstract: An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.

Abstract: A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.

Abstract: A method for reducing data-dependent loading on a voltage reference pre-charges a capacitor of the capacitive digital-to-analog converter to configure the capacitor in a pre-charged state during a first interval. The method selectively discharges the capacitor from the pre-charged state according to a value of an input digital signal to configure the capacitor in a selectively discharged state during a second interval. The method holds an output node of the capacitive digital-to-analog converter at a reset voltage level during the first interval and the second interval. The output node is coupled to a first terminal of the capacitor. The method discharges any remaining charge on the capacitor and providing an output voltage signal to an output node of the capacitive digital-to-analog converter according to the selectively discharged state during a third interval. The output voltage signal has a voltage level corresponding to a value of the input digital signal.

Abstract: A method includes alternately coupling a selected one of a plurality of current sources and two or more of the plurality of current sources to a first terminal of a bipolar device during first and second phases of a modulator cycle of a plurality of modulator cycles. The method further includes providing sampled voltages from the first terminal of the bipolar device to a modulator to produce a modulator output signal, filtering the modulator output signal to produce a filtered output signal using a back-end filter having an impulse response, and determining a temperature in response to the filtered output signal.

Abstract: Systems and methods that may be implemented to configure a single common radio frequency (RF) radio module with multiple link layers to allow the radio module to transmit different advertisement packets at the same time using different advertisement configuration parameters. A radio module may be simultaneously configured with the multiple link layers to allow the radio module to operate using unique different advertisement parameters corresponding to each of multiple different advertisement policies, and such that the radio module may selectively transmit advertisement packets in real time using any one of the different advertisement policies.

Abstract: An oscillation circuit including a crystal interface for coupling to a crystal, a crystal amplifier that drives the crystal to establish oscillation, a memory, a timing circuit, a level detector that provides an amplitude indication when an oscillation achieves a programmable threshold, and a controller. The controller applies one or more settings including gain and activates the crystal amplifier, measures the startup time, and calculates startup energy. The startup energy is based on a bias current of the crystal amplifier, remaining system current, and the startup time. The settings may include a gain setting of the crystal amplifier and one or more thresholds used by the threshold detector. The controller adjusts the settings for multiple startups, and determines optimal settings for minimizing the startup energy. The memory stores the optimal settings along with robust settings that may be used on a one-time basis in the event of startup failure.

Abstract: An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.

Abstract: A method for operating a clock product includes generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals. The frequency metrics are generated using the reference clock signal. The method includes generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric. For each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

Abstract: In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.