Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a differencing comparator. The differencing comparator receives a differential input signal. The differencing comparator compares the differential input signal to a threshold value. The differencing comparator includes a transconductance circuit coupled to receive the differential input signal and to provide a differential output signal.

Abstract: In an example, an apparatus includes: a pass device coupled between a supply voltage node and a load circuit and to provide a regulated voltage to the load circuit in response to a control signal received at a control terminal of the pass device; a first amplifier to compare a reference voltage to the regulated voltage and to output a comparison signal at a comparison node in response to the comparison; a second amplifier having an input device having a control terminal coupled to the comparison node to receive the comparison signal and to output the control signal to the pass device based at least in part in response to the comparison signal; and a feedback circuit to provide a feedback signal to the first amplifier based at least in part on a load current of the load circuit.

Abstract: An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.

Abstract: A method includes receiving a plurality of requests to perform accesses for associated DMA channels and arbitrating the requests. The arbitration includes selectively granting a given request of the plurality of requests based at least in part on an associated fixed priority of the request and an associated priority weighting of the request. The priority weighting regulates which request or requests of the plurality of requests are considered at a given time.

Abstract: Hysteresis causes the temperature dependent frequency characteristic of the crystal of a crystal oscillator to be different when the temperature is rising from a previous colder state and when the temperature is falling from a hotter state. A rising temperature-to-frequency mapping polynomial and a falling temperature-to-frequency mapping polynomial are generated and their evaluations are weighted based on a current temperature and past temperature(s). The weighted evaluations are combined and used in temperature-based frequency compensation of the crystal oscillator.

Abstract: Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a programmable digital input signal is determined in a calibration mode and then applied to reference circuitry in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.

Abstract: Systems and methods are provided that may be implemented to selectively enable relatively higher data throughput and higher power WiFi bidirectional wireless protocol capability during times of system wireless activity, and to selectively disable the WiFi bidirectional wireless protocol and enable relatively lower data throughput and lower power wireless protocol capability during the absence of such system wireless activity. The systems and methods may be implemented to enable bi-directional wireless communication and/or external activation of a wireless device both during times of wireless device activity and during times in which wireless device activity is absent and/or a wireless device is inactive and not transmitting.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.

Abstract: A system and method of allowing a network device to receive a customized version of a reference design is disclosed. In one embodiment, many values that may be subject to customization are no longer fixed by the reference design. Rather, the reference design utilizes rewritable non-volatile memory to store a set of customization values that can be changed, based on a customer's preference. The system also includes a configuration tool, which interfaces with the network device. Using vendor-unique commands, the configuration tool is able to initialize this set of customization values to the values requested by the customer. In operation, the reference design is downloaded into the network device. The configuration tool is then used to establish the customized parameters for a particular customer. This process allows the manufacturer to create one reference design, which can be customized without the need to modify the code or recompile the source code.

Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.

Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.

Abstract: In one embodiment, a radio receiver includes: a programmable frequency synthesizer to generate a first clock signal; a first frequency divider to divide the first clock signal to generate a master clock signal; a second frequency divider to divide the master clock signal to generate a mixing signal; and a mixer to downconvert a radio frequency (RF) signal to a second frequency signal using the mixing signal. A voltage converter to couple to the radio receiver includes a switch controllable to switchably couple a first voltage to a storage device and a pulse generator to generate at least one pulse pair formed of a first pulse and a second pulse substantially identical to the first pulse, when a second voltage is less than a first threshold voltage, the second pulse separated from the first pulse by a pulse separation interval.

Abstract: In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: In one aspect, an apparatus includes: a first power amplifier to receive a first voltage signal and to output a first current; a second power amplifier to receive a second voltage signal and to output a second current; and a transformer coupled to the first power amplifier and the second power amplifier. The transformer may have multiple differential input ports to realize a controllable impedance based on a desired output power level.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.