Abstract: In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.

Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Abstract: A system and method of disseminating bootload images through a wireless network are disclosed. The central node, or server, transmits segments of the bootload image using broadcast so that all wireless network devices receive the image at the same time. The server then individually queries each wireless device to determine whether there are any segments of the image that were not received by that particular wireless device. The server then retransmits, using broadcast, any segment that was not received by any wireless device. Once every wireless device has the entire image, the server may initiate the process of installing that image.

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

Abstract: A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.

Abstract: A voltage converter includes a comparator that continuously monitors an output voltage of the voltage converter. The comparator includes a first comparator core utilizing first and second switched capacitors and a second comparator core using third and fourth switched capacitors. The first comparator core is powered down or in a refresh mode while the second comparator core is monitoring the output voltage. The second comparator core is powered down or in the refresh mode while the first comparator core is monitoring the output voltage. The first and second switched capacitors are configured in series with an amplifier stage of the first comparator core while the first comparator core is monitoring the output voltage. The refresh mode charges the first (third) and second (fourth) switched capacitors to a scaled version of the output voltage and a reference voltage less an offset voltage, respectively.

Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller parses incoming packets as they are received and generates a request signal once it is determined that the incoming packet is destined for this device. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.

Abstract: An apparatus includes a circuit that includes a communication circuit to communicate information via a link using two communication modes. In the first communication mode, the communication circuit communicates information using a communication protocol. In the second communication mode, the communication circuit communicates information without triggering communication using the communication protocol.

Abstract: An apparatus includes a first antenna coupled to a first radio frequency (RF) circuit to receive or transmit RF signals, and a second antenna coupled to a second RF circuit to receive or transmit RF signals. The apparatus further includes a first RF current blocker disposed between the first and second antennas, and a second RF current blocker disposed between the first and second antennas. The first and second RF current blockers increase isolation between the first and second antennas.

Abstract: A system for automatically detecting the PHY mode based on the incoming preamble is disclosed. The system includes a multimode demodulator, which includes a preamble detector and a demodulator. The preamble detector is used to determine when the preamble has been received and the PHY mode being used by the sending node. An indication of the PHY mode is supplied to the demodulator, which then decides the incoming bit stream in accordance with the detected PHY mode. In some embodiments, one demodulator, capable of decoding the bit stream in accordance with a plurality of PHY modes is employed. In other embodiments, the system includes a plurality of demodulators, where each is dedicated to one PHY mode.

Abstract: An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

Abstract: In embodiments of the present invention improved capabilities are described for an antenna-based detection method and system for sensing an environmental change condition. The method and system is adapted such that the states comprising the environmental change condition are capable of being determined at the location of the detection point utilizing only the magnitude component of the antenna impedance as altered by the discrete change in the environmental condition.

Abstract: A fault tolerant communication protocol transmits information across a communication channel from a transmitting device to a receiving device. The receiving device echoes back a copy of the transmitted information to the transmitting device. The transmitting device sends a first valid signal across the communication channel if the echoed information matches the transmitted information. The receiving device sends a second valid signal across the communication channel responsive to the first valid signal. The transmitting device stops sending of the first valid signal responsive to the second valid signal and the receiving device stops sending the second valid signal responsive to determining the first device has stopped sending the first valid signal. The receiving device can then update its state based on a successful transfer.

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

Abstract: A novel method of providing a locking mechanism which supports multiple operations rights is disclosed. The locking mechanism includes a policy aspect which defines which operations are allowed to access the common resource concurrently. The locking mechanism also includes the ability to allow predetermined number of tasks to access the common resource simultaneously. Furthermore, additional operations can be easily and quickly added to the mechanism.

Abstract: A method compensates for a frequency error in a communications system. The method includes detecting a received preamble sequence in a received signal. The received preamble sequence is detected based on a plurality of power estimates corresponding to a plurality of frequency bins of a received frequency domain signal and a plurality of relative phase errors corresponding to the plurality of frequency bins of the received frequency domain signal. The method includes determining the frequency error using the received preamble sequence. The method includes adjusting the receiver based on the frequency error.

Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.

Abstract: An apparatus includes a radio frequency (RF) receiver, which includes a digital signal arrival (DSA) detector to detect arrival of a transmitted signal. The DSA detector includes a signal correlator and at least one of (a) an absolute received signal strength indication (RSSI) detector; (b) a relative RSSI detector; and (c) a frequency offset detector). The RF receiver further includes a demodulator coupled to the DSA detector to demodulate a received signal and to provide a demodulated signal, and a synchronization word detector (SWD) coupled to the demodulator to receive the demodulated signal.

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a current source, to sink or source an output current, in response to a control signal, and a switch-capacitor resistor coupled to the current source. The apparatus further includes a controller coupled to derive the control signal from a voltage across the switch-capacitor resistor, the controller further to provide a switch control signal to the switch-capacitor resistor.