Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller parses incoming packets as they are received and generates a request signal once it is determined that the incoming packet is destined for this device. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: An apparatus includes a circuit that includes a communication circuit to communicate information via a link using two communication modes. In the first communication mode, the communication circuit communicates information using a communication protocol. In the second communication mode, the communication circuit communicates information without triggering communication using the communication protocol.

Abstract: A system for automatically detecting the PHY mode based on the incoming preamble is disclosed. The system includes a multimode demodulator, which includes a preamble detector and a demodulator. The preamble detector is used to determine when the preamble has been received and the PHY mode being used by the sending node. An indication of the PHY mode is supplied to the demodulator, which then decides the incoming bit stream in accordance with the detected PHY mode. In some embodiments, one demodulator, capable of decoding the bit stream in accordance with a plurality of PHY modes is employed. In other embodiments, the system includes a plurality of demodulators, where each is dedicated to one PHY mode.

Abstract: An apparatus includes a first antenna coupled to a first radio frequency (RF) circuit to receive or transmit RF signals, and a second antenna coupled to a second RF circuit to receive or transmit RF signals. The apparatus further includes a first RF current blocker disposed between the first and second antennas, and a second RF current blocker disposed between the first and second antennas. The first and second RF current blockers increase isolation between the first and second antennas.

Abstract: An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

Abstract: In embodiments of the present invention improved capabilities are described for an antenna-based detection method and system for sensing an environmental change condition. The method and system is adapted such that the states comprising the environmental change condition are capable of being determined at the location of the detection point utilizing only the magnitude component of the antenna impedance as altered by the discrete change in the environmental condition.

Abstract: A radio frequency (RF) device is provided. The RF device includes an antenna interface, a receive circuit configured to extract data from incoming signals, a playback circuit configured to associate a predefined delay with the data, a transmit circuit configured to generate outgoing signals based on the data and the predefined delay, and a control circuit configured to calculate range based in part on the predefined delay and phase differences between incoming signals and outgoing signals.

Abstract: A fault tolerant communication protocol transmits information across a communication channel from a transmitting device to a receiving device. The receiving device echoes back a copy of the transmitted information to the transmitting device. The transmitting device sends a first valid signal across the communication channel if the echoed information matches the transmitted information. The receiving device sends a second valid signal across the communication channel responsive to the first valid signal. The transmitting device stops sending of the first valid signal responsive to the second valid signal and the receiving device stops sending the second valid signal responsive to determining the first device has stopped sending the first valid signal. The receiving device can then update its state based on a successful transfer.

Abstract: A novel method of providing a locking mechanism which supports multiple operations rights is disclosed. The locking mechanism includes a policy aspect which defines which operations are allowed to access the common resource concurrently. The locking mechanism also includes the ability to allow predetermined number of tasks to access the common resource simultaneously. Furthermore, additional operations can be easily and quickly added to the mechanism.

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.

Abstract: A method compensates for a frequency error in a communications system. The method includes detecting a received preamble sequence in a received signal. The received preamble sequence is detected based on a plurality of power estimates corresponding to a plurality of frequency bins of a received frequency domain signal and a plurality of relative phase errors corresponding to the plurality of frequency bins of the received frequency domain signal. The method includes determining the frequency error using the received preamble sequence. The method includes adjusting the receiver based on the frequency error.

Abstract: An apparatus includes a radio frequency (RF) receiver, which includes a digital signal arrival (DSA) detector to detect arrival of a transmitted signal. The DSA detector includes a signal correlator and at least one of (a) an absolute received signal strength indication (RSSI) detector; (b) a relative RSSI detector; and (c) a frequency offset detector). The RF receiver further includes a demodulator coupled to the DSA detector to demodulate a received signal and to provide a demodulated signal, and a synchronization word detector (SWD) coupled to the demodulator to receive the demodulated signal.

Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a current source, to sink or source an output current, in response to a control signal, and a switch-capacitor resistor coupled to the current source. The apparatus further includes a controller coupled to derive the control signal from a voltage across the switch-capacitor resistor, the controller further to provide a switch control signal to the switch-capacitor resistor.

Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.

Abstract: Systems and methods are provided that may be implemented to adaptively control advertising and/or scanning operations on multiple advertising channels in a wireless network environment. In one example, a wireless device may monitor for wireless activity from other protocols (e.g., such as Wi-Fi or Zigbee) on the frequency of one or more of the multiple advertising channels of a first wireless network protocol, such as a BLE wireless network protocol. The wireless device may respond in real time to the detected presence of wireless activity from other protocols on one or more of the advertising channels of the first protocol by dynamically varying the identity of which advertising channels are employed at any given time for advertising and/or scanning.

Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller parses incoming packets as they are received and generates a request signal once it is determined that the incoming packet is destined for this device. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: Networks with a plurality of independent nodes are useful when the nodes can communicate with one another and with nodes and resources outside the network. The present disclosure addresses ways to encapsulate packets as they move from a sender to a receiver, and also addresses ways for speeding up messages between nodes by orderly queuing and processing of messages. The present disclosure also includes techniques for mapping nodes in a home area network to IP addresses in a local area network.

Abstract: An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.