Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract: A circuit device includes a diode bridge having a first power input and a second power input and having a first output terminal and a second output terminal. The diode bridge includes a plurality of diodes and a respective plurality of diode bypass elements associated with the plurality of diodes. The circuit device further includes a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at the first and second output terminals.

Abstract: Methods of reassembling a mesh network which has been disrupted by the unavailability of a node or a link are disclosed. Nodes continuously receive beacon messages originating from a leader node. These beacon messages may be transmitted directly by the leader node, or may have been retransmitted by an intermediate node. When a node determines that it has not received a beacon message in a certain time period, it concludes that it is now disconnected from that leader node. At this point, it may choose to act as a leader node and form a new network, or may join with another network. The determination of which network to join may be based on some indicia associated with the leader node of that network.

Abstract: Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.

Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Abstract: Systems and methods are disclosed for MCM (multiple chip module) packages having multiple stacked demodulator dies that share one or more MCM pins. The shared pins can include clock generation pins, clock input/output pins, receive signal path input pins, voltage supply pins, ground supply pins, and/or any other desired pins. In addition to reducing footprint sizes for printed circuit board (PCB) applications, the multi-demodulator MCM package embodiments described herein also allow for improved routing of connection traces on PCBs.

Abstract: In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter.

Abstract: A long-wave or medium-wave receiver receives a first signal from a first terminal of a loopstick antenna on a positive antenna input terminal of the receiver and receives a second signal from a second terminal of the loopstick antenna on a negative antenna input terminal of the receiver. The first and second signals are processed differentially in the receiver. The receiver may optionally be configured to operate in either a differential mode or a single-ended mode by setting switches to selectively connect one of the antenna input terminals to ground in single-ended mode.

Abstract: A method of efficiently disseminating various types of information throughout a mesh network is disclosed. Information is typically propagated through the network using a variety of protocols and messages. However, in one embodiment, a single message, communicates all of this information at once. The message includes data originating at the leader, which does not change as the messages are propagated through the network, as well as topology and link information that is created by the forwarding nodes. The data originating at the leader includes the identity of the leader node and a sequence number. Additionally, a version number is included by the leader which represents the state of the quasi-static information. Quasi-static information may include, for example, the identity of a node that has access to a central control system or the internet. This compact message format allows improved efficiency and use of the network.

Abstract: A radio receiver and method of operating the same are disclosed. In one embodiment, the radio receiver may include a RF receive path configured to convey a first radio signal within a first band to a radio tuning circuit. The RF receive path may be controllable using a first AGC circuit. The radio receiver may also include a loop-through path configured to convey a second radio signal within a second band between an input and an output of the radio receiver. The second band may be different from the first band. The loop-through path may be controllable using a second AGC circuit.

Abstract: In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands.

Abstract: Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Abstract: In one embodiment, a method includes determining environmental conditions associated with operation of a chip having multiple device types, accessing a table stored in the chip based on the determined environmental conditions, and dynamically operating the chip at a bias point accessed from the table based on the determined environmental conditions.

Abstract: A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

Abstract: An integrated circuit gas sensor system may include an integrated circuit having a bond pad layer and a dielectric layer formed after the bond pad layer. A conductor layer may be above the dielectric layer. The conductor layer may be utilized to form both gas sensor and humidity sensor conductor patterns, which may be planar. In one embodiment, the gas sensor is combined with a humidity sensor, the gas sensor and the humidity sensor covering more than 50% of the top surface of the integrated circuit. In one embodiment, the central region of the integrated circuit has a majority of its surface area utilized for the sensor structures, and in a more preferred embodiment has more than 80% of its surface area utilized for sensing structures. In one embodiment, resistive sensing may be utilized for the gas sensor and capacitive sensing may be utilized for the humidity sensor.

Abstract: A circuit includes a discriminator to store a threshold. The circuit further includes a comparator including a first input to receive a count, a second input to receive the threshold, and an output to provide an output signal representing a result of the comparison between the count and the threshold. The circuit also includes a controller to automatically adjust the threshold when the count exceeds a first threshold or falls below a second threshold.

Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.

Abstract: An apparatus includes a first set of circuits adapted to operate in a first mode of operation of the apparatus. The apparatus further includes a second set of circuits adapted to operate in a second mode of operation of the apparatus, where a power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. The apparatus also includes a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, and the second supply voltage powers the second set of circuits.