Abstract: Silicon semiconductor wafers are produced by: pulling a single crystal with a conical section and an adjoining cylindrical section having a diameter ?450 mm and a length of ?800 mm from a melt in a crucible, wherein in pulling the transition from the conical section to the cylindrical section, the pulling rate is at least 1.8 times higher than the average pulling rate during the pulling of the cylindrical section; cooling the growing single crystal with a cooling power of at least 20 kW; feeding heat from the side wall of the crucible to the single crystal, wherein a gap having a height of ?70 mm is present between a heat shield surrounding the single crystal and the melt surface.

Abstract: An incorrect position of a semiconductor wafer during thermal treatment in a process chamber heated by means of infrared emitters and transmissive to infrared radiation is identified, wherein the semiconductor wafer lies in a circular pocket of a rotating susceptor and is held at a predetermined temperature with the aid of the infrared emitters and a control system, and wherein thermal radiation is measured by a pyrometer, an amplitude of the fluctuations of the measurement signal is determined and an incorrect position of the semiconductor wafer is assumed if the amplitude exceeds a predetermined maximum value. The pyrometer is oriented such that the measurement spot detected by the pyrometer lies partly on the semiconductor wafer and partly outside the semiconductor wafer on the susceptor so that it is possible to identify an eccentric position of the semiconductor wafer within the pocket of the susceptor.

Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.

Abstract: A ring-shaped resistance heater for supplying heat to a growing single crystal, comprising: an upper and a lower ring, which are electrically conductively connected by means of a loop adjacent to a ring gap of the lower ring, such that the flow direction of electric current which is conducted through the rings is opposite in the rings; connecting elements which hold the upper and lower rings together at a distance; and current leads for conducting electric current through the upper and lower rings.

Abstract: A multiplicity of wafer-type workpieces are buffer stored in a device having, a frame, at least two transport elements which each circulate in a vertical direction around an upper and a lower deflection device connected to the frame and are provided, at uniform intervals, with a multiplicity of bearing areas for the horizontal mounting of workpieces, wherein at least one of the deflection devices of each transport element is driven and a free space is situated between the transport elements, a loading position between the upper deflection devices at which a workpiece can be placed onto corresponding bearing areas, and a stationary removal device below the loading position, comprising a horizontal transport device, the first end of which lies within the free space between the transport elements. The invention also relates to a method for buffer-storing a multiplicity of wafer-type workpieces using the abovementioned device.

Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.

Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back arc then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1 ?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.

Abstract: Semiconductor wafer provided with a strain-relaxed layer of Si1-xGex, are polished in a first step of mechanical machining of the Si1-xGex layer of the semiconductor wafer in a polishing machine using a polishing pad containing fixedly bonded abrasive materials having a particle size of 0.55 ?m or less, and also a second step of a chemomechanical machining of the previously mechanically machined Si1-xGex layer of the semiconductor wafer using a polishing pad and with supply of a polishing agent slurry containing abrasive materials.

Abstract: Silicon semiconductor wafers are produced by: pulling a single crystal with a conical section and an adjoining cylindrical section having a diameter ?450 mm and a length of ?800 mm from a melt in a crucible, wherein in pulling the transition from the conical section to the cylindrical section, the pulling rate is at least 1.8 times higher than the average pulling rate during the pulling of the cylindrical section; cooling the growing single crystal with a cooling power of at least 20 kW; feeding heat from the side wall of the crucible to the single crystal, wherein a gap having a height of ?70 mm is present between a heat shield surrounding the single crystal and the melt surface.

Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

Abstract: Epitaxially coated silicon wafers have a rounded and polished edge region and a region adjacent to the edge having a width of 3 mm on the front and rear sides, a surface roughness in edge region of 0.1-1.5 nm RMS relative to a spatial wavelength range of 10-80 ?m, and a variation of surface roughness of 1-10%. The wafer edges, after polishing, are examined for defects and roughness at the edge and surrounding region. Silicon wafers having a surface roughness of less than 1 nm RMS are pretreated in single wafer epitaxy reactors, first in a hydrogen atmosphere at a flow rate of 1-100 slm and in a second step, an etching medium with a flow rate of 0.5-5 slm is conducted onto the edge region of the wafer by a gas distribution device. The wafer is then epitaxially coated.

Abstract: A susceptor for supporting a semiconductor wafer during deposition of a layer on a front side of the semiconductor wafer, the semiconductor wafer having a diameter D and, at its edge, a notch having a depth T, comprising: a ring-shaped placement area having an internal diameter d for the placement of the semiconductor wafer in the edge region of a rear side of the semiconductor wafer, wherein, with the semiconductor wafer having been placed, the relationship (D?d)/2<T is satisfied; and a protrusion of the area for the placement of semiconductor wafer in the region of the notch of the semiconductor wafer extending the placement area inward, and which completely underlays the notch of the semiconductor wafer.

Abstract: An apparatus for depositing a material layer originating from process gas on a substrate wafer, contains: a reactor chamber delimited by an upper dome, a lower dome, and a side wall; a susceptor for holding the substrate wafer during the deposition of the material layer; a preheating ring surrounding the susceptor; a liner, on which the preheating ring is supported in a centered position wherein a gap having a uniform width is present between the preheating ring and the susceptor; and a spacer acting between the liner and the preheating ring, the spacer keeping the preheating ring in the centered position and providing a distance ? between the preheating ring and the liner.

Abstract: A method for cutting a workpiece with a wire saw includes running at least one saw wire in a lateral direction. A first abrasive grain slurry is supplied to the saw wire on two points that are separated by a predetermined distance in a lateral direction. Cutting of the workpiece is started by moving at least one of the workpiece and the saw wire relative to the other and bringing the workpiece into contact with the saw wire from above at a location between the two points on the saw wire where the first abrasive grain slurry is supplied. A second abrasive grain slurry is supplied to a part of an area where the saw wire meshes with the workpiece.

Abstract: A method for depositing a layer on a semiconductor wafer using chemical vapor deposition (CVD). The method includes providing a chamber having an inlet opening and an outlet opening and a channel joining the inlet opening and the outlet opening, wherein the channel is bounded at the bottom by a plane and at the top by a window transmissive to thermal radiation. A semiconductor wafer is disposed so that a surface of the semiconductor lies in the plane, wherein the window has a center region disposed over the semiconductor wafer and an edge region surrounding the center region and not disposed over the semiconductor wafer. A distance between the plane and the window varies across the chamber, the distance being greater at the edge region than at the center region. A tangent applied to a radial profile of the distance at a boundary between the center region and the edge region forms an angle with the plane of not less than 15° and not more than 25°.

Abstract: A method for simultaneously cutting a compound rod of semiconductor material into a multiplicity of wafers. The method includes selecting a first workpiece and a second workpiece, each having two end surfaces; grinding at least one of the two end surfaces of each workpiece so as to create a ground end surface on each workpiece; cementing the ground end surface of the first workpiece to the ground end surface of second workpiece using a fastener so as to produce a compound rod piece having a longitudinal axis, wherein the fastener is disposed between the workpieces so as create a distance between the workpieces; fixing the compound rod piece in a longitudinal direction on a mounting plate; clamping the mounting plate with the compound rod piece in a wire saw; and cutting the compound rod piece perpendicularly to the longitudinal axis using the wire saw.

Abstract: The present invention relates to an apparatus and a method for the fluidic inline-treatment of flat substrates with at least one process module. In particular, the invention relates to such a treatment during the gentle and controlled transport of the substrates, wherein the treatment can also just relate to the transport of the substrates. According to the invention, a process module 1 is provided which comprises a treatment chamber 2 having at least one treatment surface 7A being substantially horizontally arranged in a treatment plane 5 and being designed for the formation of a lower fluid cushion 6A, wherein two openings in the form of entry 3 and exit 4 for the linear feed-through of the substrates 22 in the same plane are assigned to the treatment surface 7A, and at least one feed device with at least one catch 10 for the controlled feed 9 of the substrates 22 within the treatment chamber 2. Furthermore, the invention provides a method using the apparatus according to the invention.

Abstract: A method for slicing wafers from a workpiece includes providing wire guide rolls each having a grooved coating with a specific thickness and providing rings at opposing ends of a first of the coatings of a respective wire guide roll. The rings are fixed exclusively to the first coating. A sawing wire including wire sections disposed in a parallel fashion is tensioned between the wire guide rolls. The wire sections of the sawing wire are moved relative to the workpiece so as to perform a sawing operation. A change in length of the first coating, brought about by a temperature change, is measured by measuring distances between sensors and the rings. The wire guide rolls are cooled in a manner dependent on the measured distances.

Abstract: A method for slicing wafers from a workpiece includes providing wire guide rolls that each have a grooved coating with a specific thickness, providing a fixed bearing respectively associated with each wire guide roll and providing a sawing wire including wire sections disposed in a parallel fashion. The wire sections are tensioned between the wire guide rolls and are moved relative to the workpiece so as to perform a sawing operation. The wire guide rolls cooled and the fixed bearings are cooled independently of the wire guide rolls.

Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.