Abstract: Power amplifier with bias adjustment circuit. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to provide a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

Abstract: Radio-frequency (RF) power amplifiers driven by boost converter. In some embodiments, a power amplification system can include a supply system configured to provide a high-voltage (HV) supply signal based on a battery voltage, and a power amplifier (PA) configured to receive the HV supply signal and amplify an RF signal. The power amplification system can further include an output path configured to route the amplified RF signal to a filter. Such an output path can be substantially free of either or both of an impedance transformation circuit and a band selection switch.

Abstract: A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

Abstract: A power amplifier die includes a semiconductor substrate, a power amplifier implemented on the semiconductor substrate, a radio-frequency input configured to receive a radio-frequency input signal having a radio-frequency component and a DC bias component, a bias circuit implemented on the semiconductor substrate, the bias circuit coupled to the power amplifier, and a bias tee circuit implemented on the semiconductor substrate, the bias tee circuit configured to receive the radio-frequency input signal and pass at least a portion of the DC component to the bias circuit and at least a portion of the radio-frequency component to the power amplifier.

Abstract: In some embodiments, a laminate substrate for mounting RF components can include a plurality of layers vertically stacked on top of each other. The laminate substrate includes a plurality of conductor pads, such that a respective conductor pad is positioned within a respective layer of the laminate substrate. The plurality of conductor pads includes an input pad on a first layer, an output pad on a second layer such that the output pad does not completely overlap with the input pad, and at least one intermediate pad between the input and output pads. The at least one intermediate pad defines a cutout reducing overlap between the at least one intermediate pad and one or more neighboring conductor pads. The laminate substrate can further include a plurality of connection features between the plurality of conductor pads to provide a signal path between the input pad and the output pad.

Abstract: A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit.

Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: Disclosed are systems and methods related to matching an impedance of the power amplifier to an impedance of the antenna in a power amplifier module that includes an amplifier circuit residing on a first semiconductor die and an output matching network (OMN) that includes a first partial OMN and a second partial OMN. The first partial OMN resides on the first semiconductor die and matches an output impedance of the amplifier circuit to an input impedance of the second partial OMN. The second partial OMN matches an output impedance of the first partial OMN with an input impedance of the antenna and is not part of the first semiconductor die.

Abstract: Systems, devices and methods related to multi-band power amplifier. In some embodiments, a power amplifier module includes a power amplifier having an output stage and configured to receive a signal. The power amplifier module also includes a first programmable harmonic termination circuit in electrical communication with the output stage of the power amplifier. The first programmable harmonic termination circuit includes a first plurality of capacitors and a first plurality of switches, with at least one of the first plurality of capacitors being in electrical communication with at least one of the first plurality of switches. The power amplifier module further includes a controller configured to modify a configuration of the first plurality of switches of the first programmable harmonic termination circuit based at least in part on a second harmonic frequency of the signal.

Abstract: A voltage regulator device is disclosed, comprising a first pin and a second pin, a regulator circuit implemented between the first pin and the second pin, one or more internal blocks configured to be powered through a supply node to facilitate operation of the regulator circuit and an internal supply circuit coupled to the first pin, the second pin, and the supply node, the internal supply circuit configured to provide a supply voltage to the supply node from either or both of the first and second pins.

Abstract: Apparatus and methods for wireless local area network (WLAN) power amplifiers are provided. In certain configurations, a WLAN power amplifier system includes a WLAN power amplifier, an output impedance matching network, and an envelope tracker. The WLAN power amplifier includes an input that receives a WLAN signal having a fundamental frequency and an output that generates an amplified WLAN signal for transmission over an antenna. The output impedance matching network is electrically connected to the output of the WLAN power amplifier, and can provide a load line impedance between 10? and 35? at the fundamental frequency. The envelope tracker receives an envelope of the WLAN signal, and controls a voltage level of a power supply of the WLAN power amplifier based on the envelope signal.

Abstract: An endpoint booster transports an optical signal from inside of a plasma etch chamber through a viewport to an optical cable outside of the plasma etch chamber. The optical signal is analyzed to determine an endpoint of a plasma process. The endpoint booster inhibits process byproducts from accumulating on the viewport during the plasma process, which increases the time between chamber cleanings. The reduction in chamber downtime for cleaning increases production throughput.

Abstract: Systems, apparatuses and methods are disclosed providing a semiconductor die comprising a semiconductor substrate and a radio-frequency (RF) switch including one or more series field-effect transistors (FETs) and one or more shunt FETs, each of the one or more series FETs and one or more shunt FETs having a respective gate node, the RF switch being configured to receive an RF signal from a power amplifier module and provide the RF signal to an antenna. The semiconductor die may further comprise an internal regulator voltage source configured to provide an internal regulator voltage when the RF switch is in a stand-by mode and shunt arm control circuitry configured to provide the internal regulator voltage to the gate nodes of the one or more shunt FETs when the RF switch is in the stand-by mode.

Abstract: Aspects of the present disclosure relate to determining the location and/or density of vias that form part of an RF isolation structure of a packaged module and the resulting RF isolation structures. From electromagnetic interference (EMI) data, locations of where via density can be increased and/or decreased without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, one or more vias can be added and/or removed from a selected area of the packaged module based on the EMI data.

Abstract: A quasi-differential amplifier with an input port and an output port. The amplifier has a phase shifter network with a first port connected to the input port, a second port, and a third port. A first amplifier has an input connected to the second port of the phase shifter network, and an output, and a second amplifier has an input connected to the third port of the phase shifter network, and an output. A balun circuit includes a first differential port connected to an output of the first amplifier, a second differential port connected to an output of the second amplifier, and a single-ended port. An output matching network is connected to the single-ended port of the balun circuit and to the output port.

Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: Testing circuit with directional coupler. A testing circuit can include a testing circuit input configured to receive an output signal from a module, the output signal having a fundamental component and a harmonic component. The testing circuit can further include a testing circuit fundamental output configured to output the fundamental component and a testing circuit harmonic output configured to output the harmonic component. The testing circuit can include a first directional coupler having a first coupler input coupled to the testing circuit input, a first transmitted output coupled to the testing circuit fundamental output, and a first coupled output coupled to the testing circuit harmonic output.

Abstract: A switching circuit for use in a frequency division duplex (FDD) spectrum re-allocated for time division duplex (TDD) applications comprises a first filter configured to filter a TDD receive signal, a duplex filter configured to filter an FDD receive signal, and a plurality of switches configured to route the FDD receive signal from an antenna through the duplex filter to receiver circuitry and to route the TDD receive signal from the antenna through the first filter to the receiver circuitry such that the FDD and TDD receive signals share the FDD spectrum.

Abstract: Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a power density translating circuit connectable between the reference device and the amplifier device, the power density matching circuit provided to substantially set a first power density associated with the reference device and a second power density associated with the amplifier device relative to one another, the first power density being a function of the first electrical supply level and the second power density being a function of the second electrical supply level.

Abstract: To reduce radio frequency losses during operation of a radio frequency integrated circuit module, the radio frequency integrated circuit module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the radio frequency current to flow around the high-resistivity material.